uaa3202m NXP Semiconductors, uaa3202m Datasheet - Page 14
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uaa3202m
Manufacturer Part Number
uaa3202m
Description
Frequency Shift Keying Fsk Receiver
Manufacturer
NXP Semiconductors
Datasheet
1.UAA3202M.pdf
(24 pages)
Philips Semiconductors
TEST INFORMATION
Tuning procedure for AC tests
1. Turn on the signal generator (f
2. Tune C6 (RF stage input) to obtain a peak voltage on test point A (see Fig.11).
3. Turn on modulation (f
4. Check that data is appearing on the data output (pin 11) and proceed with the AC tests.
AC test conditions
Table 2 Test signals
The reference signal level P
BER
Table 3 Test results
P
power from signal generator 2 at the input of the test board.
Notes
1. The power-down voltage V
2. Probe of spectrum analyzer connected to test point A.
3. Spectrum analyzer connected to the input of the test board.
1997 Aug 12
Sensitivity into pin MXIN
(see Fig.6)
Maximum input power
(see Fig.6)
Receiver turn-on time; note 1
Intercept point (mixer + PMA)
see note 2 and Fig.7
Spurious radiation see note 3
and Fig.8
1 dB compression point
(mixer + PMA) see note 2
and Fig.9
1
SIGNAL
Frequency Shift Keying (FSK) receiver
is the maximum available power from signal generator 1 at the input of the test board; P
TEST
1
2
3
3
10
TEST
2
FREQUENCY
(e.g. 15 bit errors per second for 500 bits/s).
433.92
433.92
433.82
(MHz)
i
= 433.92 MHz; f
ref
for the following tests is defined as the minimum input level in dBm to give a
PWD
modulated test
signal 1; P
modulated test
signal 1; P
(minimum P
test signal 1;
P
test signal 3;
P
test signal 3;
P
P
(minimum P
i
1
1
11
12
250 Hz square wave
= 433.92 MHz; no modulation; RF input level = 60 dBm).
alternates between operating mode ON (100 ms) and OFF (100 ms); see Fig.5.
= P
= 55 dBm
= 70 dBm;
= 45 dBm
DATA SIGNAL
ref
+ 10 dB
mod
1
1
1
max
1dB
GENERATOR
= 250 Hz square wave; f = 25 kHz; RF input level = 60 dBm).
)
94 dBm
30 dBm
)
14
test signal 2;
P
2
= P
2
1
MODULATION
no modulation
no modulation
BER
(e.g. 15 bit errors per second for 500 bits/s)
BER
(e.g. 15 bit errors per second for 500 bits/s)
check that the first 10 bits are correct; error
counting is started 10 ms after PWD
switched to operating mode: ON
IP3 = P
no spurious radiation (25 MHz
with level higher than 60 dBm
(maximum P
(P
P
power for test signals with P
respectively
FM (FSK)
1 dB
o1
+ 70 dB)
)]
3
3
1
1 dB, where P
+
10
10
1
2
spur
2
2
IM3 (dB); IP3
[P
)
2
RESULT
o2
is the maximum available
Preliminary specification
+ 45 dB (minimum
o1
, P
UAA3202M
o2
11
FREQUENCY
DEVIATION
is the output
or P
25 kHz
1 GHz)
38 dBm
12
,