at86rf525b ATMEL Corporation, at86rf525b Datasheet - Page 6

• Manufacturer Part Number: at86rf525b
• Description: 2.5ghz Wimax Transceiver
• Manufacturer: ATMEL Corporation

a capacitive load on all four-output ports (RXI1, RXI2, RXQ1, RXQ2).The CMD pin is available to
provide the common mode voltage of the Digital Output Buffer (DGB).
TX Path
The transmit low pass filter (TXLP) is band limited to meet the emission regulation for OFDM sig-
nals. THe dat signals to the four input ports (TX11, TX12, TXQ1, TXQ2) driving the TXLP should
be digital but with defined levels.
The complex filtered BB signal is up converted with IQ low-IF up converter (IQUC). A complex
driving LO source is used to minimize LO leakage. The output currents of the two mixer stages
are added together. The resulting signal drives the power amplifier control block (PAC).
The PAC is a Gilbert cell based current domain amplifier with the gain controlled by DC voltage
across the mixer core. In that way linear to logarithmic (dB) gain control is achieved.
The BB/MAC provides the gain setting vector at a separated serial interface.
Synthesizer
The Voltage Controlled Oscillator (VCO) operates at two times the Local Oscillator (LO) fre-
quency. The VCO output feeds a specialized divide-by-two module. The divider provides the
required times one LO frequency with both in-phase and quadrature components for use in the
IQ Mixer (IQMIX) and the IQ UpConverter (IQUC). The use of the divider at two times the LO
also reduces load pull on the LO frequency each time the integrated Power Amplifier (PA) is
enabled.
The VCO core is a differential double-grounded bipolar stage with the load for the VCO tank cir-
cuit made up of inductive and capacitive components in parallel. No external tuning devices are
required. A fully differential inductor is contained on-chip. The capacitive portion of the frequency
determining circuitry is made up of a binary weighted capacitor array and an analog voltage con-
trolled varactor. The radio makes use of a Hybrid Phase Lock Loop (PLL) architecture. The
coarse tuning is accomplished with the combination of Digital PLL/Binary capacitance array and
the fine tuning is accomplished using the more conventional analog portion of the PLL. This use
of coarse and fine tuning together reduces the analog VCO gain requirement. The reduction of
tuning tolerance issues and noise are a direct effect of this type of PLL. Additionally, the charac-
teristic impedance of the loop filter can be increased to reduce the charge pump current which
helps in the integration of the active loop filter on-chip. This PLL also contains both integral and
proportional charge pumps whose currents may be changed via register settings. This allows the
loop parameters to be optimized for tuning speed and noise reduction.
The fractional-N synthesizer in this radio utilizes a unique Phase Interpolation Divider (PID)
rather than the more conventional modulus divider architecture. The PID allows for very good
frequency resolution and fast tuning speed. It also has the speed and power advantages of an
asynchronous divider and is fully programmable within a restricted frequency range.
AT86RF525B [Preliminary]
6
5189A–WiMAX–9/07