ttsv02622 ETC-unknow, ttsv02622 Datasheet - Page 39

• Manufacturer Part Number: ttsv02622
• Description: Sts-24 Backplane Transceiver
• Manufacturer: ETC-unknow

June 2003
Agere Systems Inc.
Register Descriptions
Table 7. Register Description (continued)
Address
(hex)
0C
0D
0E
0F
[3:0]
[7:0]
[7:0]
[7:0]
Bit
4
5
6
7
A1 ERROR INSERT
A2 ERROR INSERT
A1/A2 ERRORS TO
PARITY CONTROL
DESCREAMBLER
ERROR INSERT
INPUT/OUTPUT
PARALLEL BUS
CONSECUTIVE
TRANSMIT B1
SCRAMBLER/
NUMBER OF
GENERATE
LINE LPBK
CONTROL
CONTROL
VALUE
VALUE
MASK
Name
[3:0]
(continued)
Device Register Blocks (continued)
CREG These three (0C, 0D, and 0E) per-device control signals
CREG 0 = No loopback.
CREG 0 = Odd parity.
CREG 0 = No Rx direction descramble/Tx direction scramble.
CREG See address 0x0C bits [3:0] description.
CREG See address 0x0C bits [3:0] description.
CREG 0 = No error insertion.
Type
are used in conjunction with the per channel A1/A2
ERROR INSERT COMMAND control bits to force A1/A2
errors in the transmit direction.
If a particular channel’s A1/A2 ERROR INSERT COM-
MAND control bit is set to the value 1, then the A1 and A2
error insert values will be inserted into that channels
respective A1 and A2 bytes. The number of consecutive
frames to be corrupted is determined by the NUMBER
OF CONSECUTIVE A1 A2 ERRORS TO GENERATE
[3:0] control bits.
The error insertion is based on a rising edge detector. As
such, the control must be set to value 0 before trying to
initiate a second A1 A2 corruption.
1 = Rx to Tx loopback on line side.
1 = Even parity.
1 = In Rx direction, descramble channel after SONET
1 = Invert corresponding bit in B1 byte.
frame recovery. In Tx direction, scramble data just
before parallel-to-serial conversion.
Reserved.
TTSV02622 STS-24 Backplane Transceiver
Description
Reset
Value
(hex)
60
00
00
00
0
1
1
39