ocx256 ETC-unknow, ocx256 Datasheet - Page 8

• Manufacturer Part Number: ocx256
• Description: Ocx256 Crosspoint Switch
• Manufacturer: ETC-unknow

OCX256 Crosspoint Switch—Advanced Datasheet
1.1 Input and Output Buffers
8
CLK
Ax
Ax
Px
Px
All of the input buffers are differential inputs with flow-through mode. The output buffers are
programmable for either flow-through or registered mode. Figure 3 shows the basic block diagram of the
input and output blocks with the sources for the output control signals (OE# and CLK). The control signals
are explained in more details in the following sections.
1.1.1 Input and Output Port Function Mode
D
OE#
Input
The following legend describes the various modes of the Input and Output Ports and the
specification used by the OCXPro™ Software.
Legend:
Ax–Switch Matrix Signal
Px–Port Signal
OE#–Output Enable (# means “Active Low”)
CLK–Clock
Symbol
Q
Px
Table 1
Ax
Ax
OE#
Figure 3
Summary for Programmable I/O Attributes for OCX256
Px
Input – The external signal is buffered from the Input Port pin
to the corresponding Switch Matrix line.
Output – The internal signal is buffered from the
corresponding Switch Matrix line to the Output Port pin. In
this mode an optional output enable (OE#) can be selected.
The default state is logic high with enable set to ON.
Registered Output – The internal signal on the Switch Matrix
line is registered by an edge-triggered register within the
Output Port. A clock source is required in this mode. An
output enable (OE#) is available but not required.
No Connect – In this mode, the output Port pin is isolated
from the Switch Matrix.
[Rev. 2.0] 3/21/02
Switch
Matrix
Input and Output Buffer Configuration
Neighbor
Next
CLK
Select
Clock
I/O Port Function
D
Q
Output Mode
Select
OE#
Fairchild Semiconductor
Output
Mnemonic
OP
RO
NC
IN