m36p0r9060e0zace Numonyx, m36p0r9060e0zace Datasheet

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m36p0r9060e0zace

Manufacturer Part Number
m36p0r9060e0zace
Description
512 Mbit X16, Multiple Bank, Multi-level, Burst Flash Memory 64 Mbit Burst Psram, 1.8v Supply, Multi-chip Package
Manufacturer
Numonyx
Datasheet
Feature summary
Flash memory
November 2007
Multi-Chip Package
– 1 die of 512 Mbit (32Mb x 16, Multiple
– 1 die of 64 Mbit (4Mb x16) PSRAM
Supply voltage
– V
– V
Electronic signature
– Manufacturer Code: 20h
– Device Code: 8819
ECOPACK® package
Synchronous / asynchronous read
– Synchronous Burst Read mode:
– Asynchronous Page Read mode
– Random Access: 96ns
Programming time
– 4.2µs typical Word program time using
Memory organization
– Multiple Bank memory array: 64 Mbit banks
– Four Extended Flash Array (EFA) Blocks of
Dual operations
– program/erase in one Bank while read in
– No delay between read and write
Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
100,000 Program/erase cycles per block
Common Flash Interface (CFI)
Bank, Multi-Level, Burst) Flash memory
108MHz, 66MHz
Buffer Enhanced Factory Program
command
64 Kbits
others
operations
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory
DDF
PPF
= 9V for fast program
= V
64 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
CCP
= V
DDQ
= 1.7 to 1.95V
Rev. 3
PSRAM
Block locking
– All Blocks locked at power-up
– Any combination of Blocks can be locked
– WP
– Absolute Write Protection with V
User-selectable operating modes
– Asynchronous modes: Random Read, and
– Synchronous modes: NOR-Flash, Full
Asynchronous Random Read
– Access time: 70ns
Asynchronous Page Read
– Page size: 4, 8 or 16 Words
– Subsequent Read within Page: 20ns
Burst Read
– Fixed length (4, 8, 16 or 32 Words) or
Low power consumption
– Active current: < 25mA
– Standby current: 140µA
– Deep Power-Down current: < 10µA
Low-power features
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) Mode
– Automatic Temperature-compensated Self-
with zero latency
Write, Page Read
Synchronous (Burst Read and Write)
Continuous
Refresh
F
for Block Lock-Down
M36P0R9060E0
TFBGA107 (ZAC)
FBGA
www.numonyx.com
PPF
= V
1/23
SS
1

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m36p0r9060e0zace Summary of contents

Page 1

... Low power consumption – Active current: < 25mA – Standby current: 140µA – Deep Power-Down current: < 10µA ■ Low-power features – Partial Array Self-Refresh (PASR) – Deep Power-Down (DPD) Mode – Automatic Temperature-compensated Self- Refresh Rev PPF SS 1/23 www.numonyx.com 1 ...

Page 2

Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

M36P0R9060E0 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

M36P0R9060E0 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

... It must be read in conjunction with the M58PRxxxJ and M69KB096AM datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from the Numonyx website: www.numonyx.com. Recommended operating conditions do not allow more than one memory to be active at the same time. ...

Page 7

M36P0R9060E0 Table 1. Signal names (1) A0-A24 DQ0-DQ15 V DDQ V PPF V DDF V CCP WAIT NC DU Flash Memory DPD F PSRAM E P ...

Page 8

Summary description Figure 2. TFBGA connections (top view through package DDQ 8/23 ...

Page 9

... Flash memory. 2.4 Clock (K) The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58PRxxxJ for the Flash memory. and Table 1., Signal ...

Page 10

Signal descriptions 2.5 Wait (WAIT) WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of ...

Page 11

M36P0R9060E0 2.11 PSRAM Chip Enable input (E The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (V ), the device is disabled, and goes automatically in low-power Standby mode or Deep IH Power-down mode, according to ...

Page 12

Signal descriptions 2.17 Deep Power-Down input (DPD The Deep Power-Down input is used to put the device in a Deep Power-Down mode. When the device is in Standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting ...

Page 13

M36P0R9060E0 2.22 V Ground the common ground reference for all voltage measurements in the Flashmemory SS (core and I/O Buffers) and PSRAM chips. It must be connected to the system ground. Note: Each Flash memory device in ...

Page 14

Functional description 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: E and E for the PSRAM. P Recommended operating conditions do ...

Page 15

M36P0R9060E0 Table 2. Main operating modes (2) Operation ( Flash Bus ( Read Flash Bus ( Write ...

Page 16

... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 3. ...

Page 17

M36P0R9060E0 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the ...

Page 18

... V means V DD DDF Table 5. Capacitance Symbol C Input Capacitance IN C Output Capacitance OUT 1. Sampled only, not 100% tested. Please refer to the M58PRxxxJ and M69KB096AM datasheets for further DC and AC characteristics values and illustrations. 18/23 DEVICE UNDER TEST CCP (1) Parameter Test Condition ...

Page 19

... M36P0R9060E0 6 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ...

Page 20

Package mechanical Table 6. Stacked TFBGA107 8x11mm - 9x12 active ball array, 0.8mm pitch, package data Symbol ddd 20/23 millimeters Typ Min Max 1.20 0.20 0.85 0.35 ...

Page 21

... Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. M36 1.7 to 1.95V ...

Page 22

... Revision 1 Initial release. Document status promoted to full Datasheet. PSRAM part changed. Flash memory component specifications 2 updated to latest version of M58PRxxxJ datasheet (V Table 3). H9 ball changed (top view through package). 3 Applied Numonyx branding. M36P0R9060E0 Changes changed in PP Figure 2: TFBGA connections ...

Page 23

... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...

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