m36p0r9070e0 STMicroelectronics, m36p0r9070e0 Datasheet - Page 11

• Manufacturer Part Number: m36p0r9070e0
• Description: 512 Mbit X16, Multiple Bank, Multi-level, Burst Flash Memory 128 Mbit Burst Psram, 1.8v Supply, Multi-chip Package
• Manufacturer: STMicroelectronics

M36P0R9070E0
2.10
2.11
2.12
2.13
2.14
2.15
2.16
Flash Reset (RP
The Reset input provides a hardware reset of the Flash memories. When Reset is at V
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I
of I
reset. When Reset is at V
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to V
PSRAM Chip Enable input (E
The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted
(V
Power-down mode.
PSRAM Write Enable (W
Write Enable, W
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
PSRAM Output Enable (G
Output Enable, G
be achieved with the common I/O data bus.
PSRAM Upper Byte Enable (UB
The Upper Byte En-able, UB
DQ15) to or from the upper part of the selected address during a Write or Read operation.
PSRAM Lower Byte Enable (LB
The Lower Byte Enable, LB
DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LB
bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as E
PSRAM Configuration Register Enable (CR
When this signal is driven High, V
Configuration Register (RCR) or the Bus configuration register (BCR).
IH
DD2
RPH
), the device is disabled, and goes automatically in low-power Standby mode or Deep
. After Reset all blocks are in the Locked state and the Configuration Register is
(refer to the M58PRxxxJ datasheet).
P
and UB
P
, controls the Bus Write operation of the PSRAM. When asserted (V
P
, provides a high speed tri-state control, allowing fast read/write cycles to
P
are disabled (High) during an operation, the device will disable the data
F
)
IH
P
, the device is in normal operation. Exiting Reset mode the
, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
P
, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
IH
, Write operations load either the value of the Refresh
P
DD2
)
P
P
)
remains Low.
. Refer to the M58PRxxxJ datasheet, for the value
P
)
P
P
)
)
P
)
Signal descriptions
IL
IL
), the
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, the