89hpes10t4bg2 Integrated Device Technology, 89hpes10t4bg2 Datasheet - Page 8

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89hpes10t4bg2

Manufacturer Part Number
89hpes10t4bg2
Description
10-lane 4-port Gen2 Pci Express Switch
Manufacturer
Integrated Device Technology
Datasheet
Pin Characteristics
© 2009 Integrated Device Technology, Inc
IDT 89HPES10T4BG2 Data Sheet
Note: Some input pads of the PES10T4BG2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
PCI Express Inter-
face
SMBus
General Purpose I/O
System Pins
Function
PE0RN[3:0]
PE0RP[3:0]
PE0TN[3:0]
PE0TP[3:0]
PE2RN[1:0]
PE2RP[1:0]
PE2TN[1:0]
PE2TP[1:0]
PE4RN[1:0]
PE4RP[1:0]
PE4TN[1:0]
PE4TP[1:0]
PE6RN[1:0]
PE6RP[1:0]
PE6TN[1:0]
PE6TP[1:0]
PEREFCLKN[0]
PEREFCLKP[0]
REFCLKM
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
GPIO[11,7:0]
CCLKDS
CCLKUS
MSMBSMODE
PERSTN
RSTHALT
SWMODE[2:0]
Pin Name
*Notice: The information in this document is subject to change without notice
Table 8 Pin Characteristics (Part 1 of 2)
Type
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
8 of 31
differential
Buffer
LVTTL
LVTTL
LVTTL
LVTTL
PCIe
2
Serial Link
Diff. Clock
High Drive
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
STI
I/O
STI,
STI
STI
STI
STI
3
Resistor
Internal
pull-down
pull-down
pull-down
pull-down
pull-up
pull-up
pull-up
pull-up
pull-up
1
Refer to Table 9
pull-up on board
pull-up on board
pull-up on board
pull-up on board
Notes
July 1, 2009

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