89hpes24nt3 Integrated Device Technology, 89hpes24nt3 Datasheet - Page 12

• Manufacturer Part Number: 89hpes24nt3
• Description: 24-lane, 3-port Pcie Inter-domain Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES24NT3 Data Sheet
JTAG
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST_N
1.
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
Signal
1
,
GPIO
GPIO[7:0]
1.
they are asynchronous.
2.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
The values for this symbol were determined by calculation, not by testing.
Signal
1
Thigh_16a,
Symbol
Tpw_16d
Tper_16a
Tlow_16a
Tdz_16c
Thld_16b
Tsu_16b
Tdo_16c
2
Symbol
2
Tpw_13b
Table 10 GPIO AC Timing Characteristics
Table 11 JTAG AC Timing Characteristics
JTAG_TCK falling
JTAG_TCK rising
Reference
2
Edge
Reference
none
none
Edge
12 of 31
None
Min Max Unit
50
Min
50.0
10.0
25.0
2.4
1.0
—
—
—
Max
25.0
20
20
—
—
—
—
ns
Reference
Diagram
Timing
Unit
ns
ns
ns
ns
ns
ns
ns
Reference
See Figure 5.
Diagram
Timing
April 11, 2007