am79c864a Advanced Micro Devices, am79c864a Datasheet - Page 43

• Manufacturer Part Number: am79c864a
• Description: Physical Layer Controller With Scrambler Plc-s
• Manufacturer: Advanced Micro Devices

path and are fed back to the Signature Generator. The
test data are input to the transmit data path via the Re-
mote Loopback MUX. The test data are fed back to the
Signature Generator before the transmit data path be-
cause the Repeat Filter, Data Stream Generator, and
Encoder act as filters which would reduce the fault cov-
erage provided by the test data. Fault coverage is ob-
tained for the Repeat Filter, Data Stream Generator,
and Encoder by separate signals fed to the Signature
Generator.
The state machines, while somewhat attached to the
data path, are more control oriented, and are not likely to
respond well to random vectors on the data paths. The
LEM, LSM, PCM, PCI, and RF state machines are
tested using scan logic. Under test mode, the state reg-
isters of the state machines, and their control bits in the
registers of the NPI are linked together to form a scan
chain. The output of the scan chain drives a bit in the
Signature Generator.
BIST is activated with the assertion of the RUN-BIST bit
in the PLC_CNTRL_A register. Upon activation, the
data path, LFSR, and Signature Generator are initial-
ized, and the latches in the scan chain are placed in
scan mode. After initialization, the LFSR and Signature
Generator are enabled, and the test proceeds.
When BIST has completed, the signature is frozen, and
may be read through the Node Processor Interface.
End of test occurs when a value of zero is reached in the
LFSR. Using a 16 bit LFSR clocked by the 80 ns BCLK it
will take approximately 5.24 ms to circulate 65535 test
patterns through the chip. An interrupt to the node proc-
essor after RUN_BIST has been asserted, signifies the
completion of the PLC-S self test. This interrupt is
cleared by clearing the RUN_BIST bit in the
PLC_CNTRL_A
INTR_EVENT register). BIST is aborted if the
RUN_BIST bit is cleared by writing a zero in the RUN_
BIST bit in the PLC_CNTRL_A register before BIST
completes.
Counter Segmentation Test Mode
The counters (including all timers) in the PLC-S are de-
signed in such a way, that under Counter Segmentation
Test Mode, they break apart into several 4 bit counters.
For example, in Counter Segmentation Test Mode, a
16-bit counter becomes four 4-bit counters. These 4-bit
counters in parallel, allow the counters to be tested in 2
= 16 cycles, as opposed to 2
counter.
register
16
(NOT
= 65536 cycles for a 16-bit
by
reading
P R E L I M I N A R Y
Am79C864A
the
4
Since counter test requires the ability to control the
BCLK, this test is not intended for any board level tests
or diagnostics. This is a factory test only.
Boundary Scan Test Mode
In Boundary Scan Test Mode, most of the chip input and
output latches are linked together to form a scan chain.
While this complements BIST, which does not test these
latches, the main purpose of this test mode is for board
testing. In this mode the I/O latches of the various chips
on the board are linked into a large scan chain. By
serially shifting data into the scan chain (Boundary Scan
Serial Test Mode), then clocking the data in parallel
(Normal or Boundary Scan Parallel Test Mode) and then
serially shifting the data out, the I/O latches and inter-
connections between the various chips can be tested.
The order of pins in the scan chain is shown in Table 19.
The pin TEST 0 is the scan chain input and the pin
SCANO is the scan chain output. The pins RST, LSCLK,
BCLK, NPCLK, RSCLK, RRSCLK, EBFERR, LPBCK,
SCRM, SDO, LSR 2–0, ULSB, ENCOFF, TEST 2–0,
PTSTO, NPADDR 4–0, INT, CS, and NPRW are not in-
cluded in the scan chain. Note that only the output por-
tion of the NP 15–0 bus is in the scan chain. BCLK is
used for clocking.
Table 19. Boundary Scan Chain Order
RDAT0
to
RDAT4
FOTOFF
TDAT4
to
TDAT0
TX0
to
TX9
TXPAR
RXPAR
RX9
to
RX0
NP 15
to
NP 0
Pin
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
Input
Input
Input
Input
AMD
3-45