zl30230 Zarlink Semiconductor, zl30230 Datasheet

zl30230

Manufacturer Part Number

zl30230

Description

Four Channel Universal Clock Generator

Manufacturer

Zarlink Semiconductor

Datasheet

1.ZL30230.pdf (4 pages)

Current page: 1 of 4
Download datasheet (85Kb)

Features

•

Operates from a single crystal resonator, clock

oscillator or voltage controlled oscillator

Four independently programmable clock

synthesizers generate any clock rate from 1 kHz to

720 MHz

Precision synthesizers generate clocks with jitter

below 0.7 ps RMS for 10 G PHYs

General purpose synthesizers generate a wide

range of digital bus clocks

Supports programmable frequency offsets for clock

margining; or for use as a digitally controlled

oscillator

Eight LVPECL outputs; max rate 720 MHz

Four LVCMOS outputs; max rate 160 MHz

Eight outputs configurable as LVCMOS at

3.3/2.5/1.8 or 1.5 V, max rate160 MHz; or

LVDS/LVPECL/HCSL, max rate 350 MHz

Dynamically Configurable via SPI/I2C interface

JTAG

Osco

Osci

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL30230

Master

Clock

pwr_b

JTAG

GPIO

Configuration

and Status

Figure 1 - Functional Block Diagram

SPI / I

Zarlink Semiconductor Inc.

Clock Generator 1 (Precision)

Clock Generator 3 (General Purpose)

Clock Generator 0 (Precision)

Clock Generator 2 (General Purpose)

Fs= Bs

Four

Synthesizer 1

Synthesizer 3

Synthesizer 0

Synthesizer 2

*Ks

*16*Ms

*8*Ms

Applications

•

Channel Universal Clock Generator

ZL30230GGG

ZL30230GGG2

/Ns

Timing for NPUs, FPGAs, Ethernet switches and

PCIe switches

Timing for 10 Gigabit CDRs, Rapid-IO, PCIe,

Serial MII, Star Fabric, Fibre Channel, XAUI

Processor clock, Processor bus clock, SDRAM

clock, DDR clock

Div C

Div D

Div A

Div B

Div C

Div D

Div A

Div B

Div A

Div B

Div C

Div D

Div A

Div B

Div C

Div D

*Pb Free Tin/Silver/Copper

Ordering Information

Single Ended

Differential /

Single Ended

LVCMOS

Outputs

LVPECL

Differential /

Outputs

LVCMOS

Outputs

LVPECL

Outputs

-40

100 Pin CABGA

C to +85

Short Form Data Sheet

hpdiff0_p/n

hpdiff1_p/n

hpdiff2_p/n

hpdiff3_p/n

hpdiff4_p/n

hpdiff5_p/n

hpdiff6_p/n

hpdiff7_p/n

hpoutclk0

hpoutclk1

hpoutclk2

hpoutclk3

outclk0

outclk1

outclk2

outclk3

outclk4

outclk5

outclk6

outclk7

ZL30230

Trays

April 2010

Related parts for zl30230

zl30230 Summary of contents

Page 1

... Div C Configuration Div D and Status Div D SPI / Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30230 Short Form Data Sheet April 2010 Ordering Information 100 Pin CABGA Trays * 100 Pin CABGA Trays +85 C hpdiff0_p/n Outputs hpdiff1_p/n ...

Page 2

... The free run synchronization solution allows designers to replace multiple, costly components with a highly integrated and programmable, single- chip solution. The ZL30230 device generates clocks from a single crystal, allowing designers to replace numerous oscillators traditionally used to provide timing for various components with one chip. ZL30230 2 Zarlink Semiconductor Inc ...

Page 3

... Mechanical Drawing ZL30230 3 Zarlink Semiconductor Inc. Short Form Data Sheet ...

Page 4

... Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE ZL30230 visit our Web Site at www.zarlink.com C Patent rights to use these components ...

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