zl30342 Zarlink Semiconductor, zl30342 Datasheet
zl30342
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zl30342 Summary of contents
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... Client holdover when Server packet connectivity is lost osci osco ref DPLL Programmable sync mode lock hold 2 C/SPI I Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30342 Data Sheet June 2011 Ordering Information 64 Pin CABGA Trays 64 Pin CABGA* Trays +85 C SONET / diff Ethernet apll_clk ...
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... DSLAM and RT-DSLAM Description The ZL30342 is a member of a family of footprint-compatible devices offering the full range of features required for timing and synchronization across packet networks. Mechanism and Clock Generation for Synchronization using IEEE-1588. They work seamlessly with Time Stamp solutions from all the major Switch/PHY NPU/CPU vendors. ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...