zl30122 Zarlink Semiconductor, zl30122 Datasheet - Page 9

• Manufacturer Part Number: zl30122
• Description: Sonet/sdh Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

1.0
The ZL30122 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and
synchronization for network interface cards. The DPLL is capable of locking to one of three input references and
provides a wide variety of synchronized output clocks and frame pulses.
1.1
The Digital Phase-Locked Loop synchronizes to one of the qualified references and provides automatic or
manual hitless reference switching and a holdover function when no qualified references are available. It
provides a highly configurable set of features which are configurable through the serial interface. A summary of
these features are shown in Table 1.
Modes of Operation
Loop Bandwidth
Phase Slope Limiting
Pull-in Range
Reference Inputs
Sync Inputs
Input Reference Frequencies
Supported Sync Input
Frequencies
Input Reference
Selection/Switching
Hitless Reference Switching
Output Clocks
Output Frame Pulses
Supported Output Clock
Frequencies
Supported Output Frame
Pulse Frequencies
External Pins Status
Indicators
1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or
greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the
loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz.
DPLL Features
Functional Description
Feature
Free-run, Normal (locked), Holdover
User selectable: 14 Hz, 28 Hz, or wideband
User selectable: 885 ns/s, 7.5 2s/s, 61 2s/s, or unlimited
Fixed: 130 ppm
Ref0, Ref1, Ref2
Sync0, Sync1, Sync2
2 kHz, N * 8 kHz up to 77.76 MHz
166.67 Hz, 400 Hz, 1 kHz, 2 kHz, 8 kHz, 64 kHz.
Automatic (based on programmable priority and revertiveness), or manual
selection
Can be enabled or disabled
diff_p/n, sdh_clk, p_clk
sdh_fp, p_fp synchronized to active sync reference.
As listed in Table 4
As listed in Table 4
Lock, Holdover
Table 1 - DPLL Features
Zarlink Semiconductor Inc.
ZL30122
9
DPLL
1
(890 Hz / 56 Hz / 14 Hz)
Data Sheet