zl30121 Zarlink Semiconductor, zl30121 Datasheet - Page 24

• Manufacturer Part Number: zl30121
• Description: Sonet/sdh Low Jitter System Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
3A
3B
3C
3D
3E
31
32
33
34
35
36
37
38
39
3F
40
41
42
43
dpll2_ref_pri_ctrl_0
dpll2_ref_pri_ctrl_1
dpll2_ref_pri_ctrl_2
dpll2_ref_pri_ctrl_3
dpll2_lock_holdover_status
p0_enable
p0_run
p0_freq_0
p0_freq_1
p0_clk0_offset90
p0_clk1_div
p0_clk1_offset90
p0_offset_fine
p0_fp0_freq
p0_fp0_type
p0_fp0_fine_offset_0
p0_fp0_fine_offset_1
p0_fp0_coarse_offset
p0_fp1_freq
Register
Name
Table 5 - Register Map (continued)
Reset
Value
(Hex)
3E
10
32
54
76
04
8F
0F
00
01
00
00
00
05
83
00
00
00
05
Zarlink Semiconductor Inc.
P0 Configuration Registers
ZL30121
Control register for the ref4 and re5 priority
Control register to enable p0_clk0, p0_clk1,
Control register for the [7:0] bits of the N of
Control register for the p0_clk0 phase position
Control register for the p0_clk1 frequency
Control register for the output/output phase
Control register to select the p0_fp0 frame
Bits [7:0] of the programmable frame pulse
Programmable frame pulse phase offset in
Control register for the ref0 and ref1 priority
values
Control register for the ref2 and ref3 priority
values
values
Control register for the ref6 and ref7 priority
values
DPLL2 lock and holdover status register
p0_fp0, p0_fp1, the P0 synthesizer and select
the source
Control register to generate p0_clk0, p0_clk1,
p0_fp0 and p0_fp1
N*8k clk0
Control register for the [13:8] bits of the N of
N*8k clk0
coarse tuning
selection
Control register for the p0_clk1 phase position
coarse tuning
alignment fine tuning for p0 path
pulse frequency
Control register to select fp0 type
phase offset in multiples of 1/262.14 MHz
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
multiples of 8 kHz cycles
Control register to select p0_fp1 frame pulse
frequency
24
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R