zl30131 Zarlink Semiconductor, zl30131 Datasheet - Page 5

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zl30131

Manufacturer Part Number
zl30131
Description
Oc-192/stm-64 Sonet/sdh/10gbe Network Interface Synchronizer
Manufacturer
Zarlink Semiconductor
Datasheet

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Master Clock
Miscellaneous
Power and Ground
Pin #
H10
E10
C10
F10
C5
H7
G3
D1
D9
G8
G9
H6
H8
H2
K4
K5
B5
K6
E4
E8
F4
A5
A8
B7
B8
J6
J8
J9
J3
AV
V
Name
AV
osco
V
osci
tms
CORE
NC
IC
IC
CORE
DD
DD
Type
I/O
I
O
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
I
u
Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
then it should be left unconnected.
Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz
reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of
the clock at this input determines the free-run accuracy and the long term
holdover stability of the output clocks.
Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected
when the osci pin is connected to a clock oscillator.
Internal Connection. Connect to ground.
Internal Connection. Leave unconnected.
No Connection. Leave Unconnected.
Positive Supply Voltage. +3.3V
Positive Supply Voltage. +1.8V
Positive Analog Supply Voltage. +3.3V
Positive Analog Supply Voltage. +1.8V
Zarlink Semiconductor Inc.
ZL30131
8
DC
DC
Description
nominal.
nominal.
DC
DC
nominal.
nominal.
Short Form Data Sheet
DD
. If this pin is not used

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