zl30130 Zarlink Semiconductor, zl30130 Datasheet - Page 8

• Manufacturer Part Number: zl30130
• Description: Oc-12/stm-4 Sonet/sdh/gbe Stratum 2/3/3e System Synchronizer/sets
• Manufacturer: Zarlink Semiconductor

2.0
The ZL30130 SONET/SDH/GbE Stratum 2/3E/3 System Synchronizer and SETS device is a highly integrated
device that provides all of the functionality that is required for a central timing card in carrier grade network
equipment. The basic functions of a central timing card include:
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In a typical application, the main timing path uses DPLL1 to synchronize to either an external BITS source or to a
recovered line timed source. DPLL1 monitors all references and automatically selects the best available reference
based on configurable priority and revertive properties. DPLL1 provides the wander filtering function and the P0
synthesizer generates a jitter filtered clock and frame pulse for the system timing bus which supplies all line cards
with a common timing reference. A derived output timing path using DPLL2 is available to support the SETS
function. In this case DPLL2 uses a filter above 10 Hz to prevent it from filtering wander.
Input reference monitoring for both frequency accuracy and phase irregularities
Automatic input reference selection
Support of both external timing and line timing modes
Hitless reference switching
Wander and jitter filtering
Optional Input phase transient filtering (Stratum 3E phase build-out)
Master/slave crossover for minimizing phase alignment between redundant timing cards
Independent derived output timing path for support of the SETS functionality
High Level Overview
Central
Timing
Card
P
DPLL2
T4
Derived
Output
P1
A
PHY
Figure 2 - Typical Application of the ZL30130
DPLL
Tx
P
ZL30130
DPLL1
SONET/SDH
T0
B
Line Card
P0
ZL30117
S
Line Recovered Timing
A
Zarlink Semiconductor Inc.
System Timing Bus
ZL30130
BITS A
11
BITS B
Line Card
B
ZL30136
GbE
A
ZL30130
DPLL
DPLL2
P0
P
Tx
T0
PHY
B
S
Derived
S
Output
P1
DPLL1
T4
Backplane
Short Form Data Sheet
Telecom
Central
Timing
Card