zl30110 Zarlink Semiconductor, zl30110 Datasheet - Page 10

• Manufacturer Part Number: zl30110
• Description: Telecom Rate Conversion Dpll
• Manufacturer: Zarlink Semiconductor

4.0
The ZL30110 has two possible modes of operation; Normal, and Freerun. The ZL30110 starts up in Freerun mode,
it automatically transitions to Normal mode if a valid reference is available and transitions to Freerun mode if the
reference fails.
4.1
Freerun mode is typically used when an independent clock source is required or immediately following system
power-up before synchronization is achieved.
In Freerun mode, the ZL30110 provides timing and synchronization signals which are based on the master clock
frequency (supplied to OSCi pin) only and are not synchronized to the reference input signals.
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a
is required, the master clock must also be
Freerun Mode is also used for short durations while system synchronization is temporarily disrupted. The accuracy
of the output clock during these input reference disruptions is better than the accuracy of the master clock (OSCi),
but it is off compared to the reference before disruptions.
4.2
Normal mode is typically used when a system clock source, synchronized to the network is required. In Normal
mode, the ZL30110 provides timing synchronization signals, which are synchronized to the input (REF). The input
reference signal may have a nominal frequency of 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz. The frequency of
the reference inputs are automatically detected by the reference monitors.
When the ZL30110 comes out of RESET it will initially go into Freerun mode and generate a clock with the accuracy
of its freerunning local oscillator (see Figure 4). If the ZL30110 determines that its selected reference is disrupted
(see Figure 3), it will remain in Freerun until the selected reference is no longer disrupted. If the ZL30110
determines that the reference is not disrupted (see Figure 3) then the state machine will cause the DPLL to recover
from Freerun and transition to Normal mode.
When the ZL30110 is operating in Normal mode, if it determines that the input reference is disrupted (Figure 3) then
its state machine will cause it to automatically go to Freerun mode. When the ZL30110 determines that its selected
reference is not disrupted then the state machine will cause the DPLL to recover from Freerun and transition to
Normal mode.
Freerun Mode
Normal Mode
DPLL Modes of Operation
RST
Freerun
Figure 4 - DPLL Mode Switching
±
32 ppm. See Applications - Section 6.2, “Master Clock“.
Zarlink Semiconductor Inc.
ZL30110
REF_FAIL=0
REF_FAIL=1
10
Normal
±
32 ppm output clock
Data Sheet