zl30101 Zarlink Semiconductor, zl30101 Datasheet - Page 8

• Manufacturer Part Number: zl30101
• Description: T1/e1 Stratum 3 System Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description
2.2
Pin #
10
12
13
14
15
16
17
18
11
1
2
3
4
5
6
7
8
9
Pin Description
MODE_SEL0 Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode
MODE_SEL1 Mode Select 1 (Input). See MODE_SEL0 pin description.
HOLDOVER
REF_FAIL0
REF_FAIL1
AV
V
V
Name
LOCK
TRST
GND
GND
HMS
TDO
TMS
TCK
CORE
CORE
TDI
CORE
IC
Ground. 0 V.
Positive Supply Voltage. +1.8 V
Lock Indicator (Output). This output goes to a logic high when the PLL is frequency
locked to the selected input reference.
Holdover (Output). This output goes to a logic high whenever the PLL goes into
holdover mode.
Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0
reference frequency has exceeded the out-of-range limit or that it is exhibiting abrupt
phase or frequency changes.
Internal bonding Connection. Leave unconnected.
Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1
reference frequency has exceeded the out-of-range limit or that it is exhibiting abrupt
phase or frequency changes.
Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge
of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP
controller. This pin is internally pulled up to V
left unconnected.
Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure that
the device is in the normal functional state. This pin is internally pulled up to V
this pin is not used then it should be connected to GND.
Test Clock (Input): Provides the clock to the JTAG test logic. If this pin is not used then it
should be pulled down to GND.
Positive Supply Voltage. +1.8 V
Ground. 0 V.
Positive Analog Supply Voltage. +1.8 V
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this
pin. This pin is internally pulled up to V
unconnected.
Hitless Mode Switching (Input). The HMS circuit controls phase accumulation during
the transition from Holdover or Freerun mode to Normal mode on the same reference. A
logic low at this pin will cause the ZL30101 to maintain the delay stored in the TIE
Corrector Circuit when it transitions from Holdover or Freerun mode to Normal mode. A
logic high on this pin will cause the ZL30101 to measure a new delay for its TIE Corrector
Circuit thereby minimizing the output phase movement when it transitions from Holdover
or Freerun mode to Normal mode.
(Normal, Holdover or Freerun) of operation, see Table 3 on page 18.
Zarlink Semiconductor Inc.
ZL30101
8
DC
DC
nominal.
nominal.
Description
DD
. If this pin is not used then it should be left
DC
DD
nominal.
. If this pin is not used then it should be
Data Sheet
DD
. If