zl30105 Zarlink Semiconductor, zl30105 Datasheet - Page 10

• Manufacturer Part Number: zl30105
• Description: Stratum 3 Redundant System Clock Synchronizer For T1/e1/sdh, Advanced Tca And H.110
• Manufacturer: Zarlink Semiconductor

Pin #
42
43
44
45
46
47
48
49
50
51
52
53
54
55
REF_SEL0
REF_SEL1
C4/C65o
C8/C32o
F8/F32o
F4/F65o
AGND
Name
REF0
AV
AV
C16o
F16o
C2o
IC
DD
DD
Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at
2.048 Mbit/s, 4.096 Mbit/s or 65.536 MHz (ST-BUS 65.536 Mbit/s). The output frequency
is selected via the OUT_SEL2 pin, see Table 3 on page 21.
Clock 8.192 MHz or 32.768 MHz (Output). This output is used for ST-BUS and GCI
operation at 8.192 Mb/s or for operation with a 32.768 MHz clock. The output frequency
is selected via the OUT_SEL2 pin, see Table 3 on page 21.
In C8 mode, this clock output pad uses an included Schmitt input as a PLL feedback
path; proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
Positive Analog Supply Voltage. +3.3 V
Positive Analog Supply Voltage. +3.3 V
Clock 2.048 MHz (Output). This output is used for standard E1 interface timing and for
ST-BUS operation at 2.048 Mbit/s.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
Clock 16.384 MHz (Output). This output is used for ST-BUS operation with a
16.384 MHz clock.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
Frame Pulse (Output). This is an 8 kHz 122 ns active high framing pulse or it is an 8 kHz
31 ns active high framing pulse, which marks the beginning of a frame. The pulse width is
selected via the OUT_SEL2 pin, see Table 3 on page 21.
Frame Pulse ST-BUS 2.048 Mbit/s or ST-BUS at 65.536 MHz clock (Output). This
output is an 8 kHz 244 ns active low framing pulse which marks the beginning of an
ST-BUS frame. This is typically used for ST-BUS operation at 2.048 Mbit/s and
4.096 Mbit/s. Or this output is an 8 kHz 15 ns active low framing pulse, typically used for
ST-BUS operation with a clock rate of 65.536 MHz. The pulse width is selected via the
OUT_SEL2 pin, see Table 3 on page 21.
Frame Pulse ST-BUS 8.192 Mbit/s (Output). This is an 8 kHz 61 ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mbit/s.
Analog Ground. 0 V
Internal Connection. Connect this pin to ground.
Reference Select 0 (Input/Output). In the manual mode of operation, REF_SEL0 is an
input. As an input REF_SEL0 combined with REF_SEL1 selects the reference input that
is used for synchronization, see Table 6 on page 24.
In the Automatic mode of operation, REFSEL0 is an output indicating which of the input
references is the being selected. This pin is internally pulled down to GND.
Reference Select 1 (Input/Output). See REF_SEL0 pin description.
Reference (Input). This is one of three (REF0, REF1 and REF2) input reference sources
used for synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz,
1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. This pin is internally
pulled down to GND.
Zarlink Semiconductor Inc.
ZL30105
10
Description
DC
DC
nominal
nominal
Data Sheet