ml2280 Microsemi Corporation, ml2280 Datasheet - Page 10

• Manufacturer Part Number: ml2280
• Description: Serial 8-bit Converters
• Manufacturer: Microsemi Corporation

ML2280, ML2283
FUNCTIONAL DESCRIPTION
MULTIPLEXER ADDRESSING
The design of these converters utilizes a sample data
comparator structure which provides for a differential analog
input to be converted by a successive approximation routine.
The actual voltage converted is always the difference
between an assigned “+” input terminal and a “–” input
terminal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned “+” input is less than the “–”
input, the converter responds with an all zeros output code.
A unique input multiplexing scheme has been utilized
to provide multiple analog channels with software
configurable single ended, differential, or pseudo
differential options.
A particular input configuration is assigned during the
MUX addressing sequence, prior to the start of a
conversion. The MUX address selects which of the analog
inputs are to be enabled and whether this input is single
ended or differential. In the differential case, it also assigns
the polarity of the analog channels. Differential inputs are
restricted to adjacent channel pairs. For example, channel
0 and channel 1 may be selected as a different pair but
channel 0 or channel 1 cannot act differentially with any
other channel. In addition to selecting the differential
mode, the sign may also be selected. Channel 0 may be
selected as the positive input and channel 1 as the
negative input or vice versa. This programmability is
illustrated by the MUX addressing codes shown in Table 1.
The MUX address is shifted into the converter via the DI
input. Since the ML2280 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.
Since the input configuration is under software control, it
can be modified, as required, at each conversion. A
channel can be treated as a single-ended, ground
referenced input for one conversion; then it can be
reconfigured as part of a differential channel for another
conversion. Figure 7 illustrates these different input modes.
DIGITAL INTERFACE
The block diagram and timing diagrams in Figures 2-5
illustrate how a conversion sequence is performed.
A conversion is initiated when CS is pulsed low. This line
must me held low for the entire conversion. The converter is
now waiting for a start bit and its MUX assignment word.
A clock is applied to the CLK input. On each rising edge
of the clock, the data on DI is clocked into the MUX
address shift register. The start bit is the first logic “1” that
appears on the DI input (all leading edge zeros are
ignored). After the start bit, the device clocks in the next 2
to 4 bits for the MUX assignment word.
10
SINGLE-ENDED MUX MODE
DIFFERENTIAL MUX MODE
Figure 7. Analog Input Multiplexer Functional Options
SGL/ ODD/
SGL/ ODD/
DIF
DIF
0
1
2
3
4 Single-Ended
1
1
1
1
0
0
0
0
Table 1. ML2283 MUX Addressing 4 Single-Ended
M
M
UX ADDRESS
UX ADDRESS
+
+
+
+
AGND
SIGN
SIGN
0
0
1
1
0
0
1
1
0, 1
SELECT
SELECT
or 2 Differential Channel
1
0
1
0
1
1
0
1
0
1
2
3
Mixed Mode
for ML2288
+
-
+
+
AGND
+
+
0
0
–
0, 1
2, 3
CHANNEL#
CHANNEL#
COM is internally tied to AGND
+
+
1
1
–
2 Differential
+ (–)
– (+)
+ (–)
– (+)
2
+
2
+
–
3
+
3
–
+