msm7617 Oki Semiconductor, msm7617 Datasheet - Page 11

• Manufacturer Part Number: msm7617
• Description: 2-channel Echo Canceler
• Manufacturer: Oki Semiconductor

¡ Semiconductor
PIN DESCRIPTIONS (Continued)
Pin
43
46
47
48
49
50
51
52
Symbol
RGC20
RGC21
CLKIN
WDT2
(PLL)
(PLL)
TST
V
DF2
V
DD
SS
Type
O
O
O
I
I
I
I
Not used. Leave this pin open.
Basic clock input pin.
Input a clock 18 to 20 MHz. Use 19.2 MHz if using internal synchronization
signals (SYNCO, SCKO).
Power supply for PLL circuit that uses the basic clock.
Insert a 0.1mF capacitor with excellent high frequency characteristics
between V
Ground for PLL circuit that uses the basic clock.
Insert a 0.1mF capacitor with excellent high frequency characteristics
between V
Not used. Leave this pin open.
Tone disabler flag output pin for channel 2.
This pin outputs a disable flag when the ECDM pins are used for tone
disabler.
R input level control pins for channel 2 (refer to the block diagram).
Excessive input (PCM level is at maximum value) causes a malfunction.
Use these pins when there is a possibility of excessive input.
RGC21
"H": Echo canceler disabled
"L": Echo canceler enabled
0
0
1
1
RGC20
DD
DD
0
1
0
1
(PLL) and V
(PLL) and V
Level Control Mode
Off
GC: On (control level = –20 dBm0)
By the R gain controller, levels from –20 to –11.5 dBm0
will be suppressed to –20 dBm0 and those above –11.5
dBm0 will always be attenuated by 8.5 dB. This is
effective to prevent excessive input and howling for
hands-free applications.
Inhibited
±6LR: On
Apply –6 dB to excessive inputs using the level
adjuster provided on R and S I/O. Since +6 dB also
is applied at the output, the total level will not
change, making this effective against line echo.
SS
SS
(PLL).
(PLL).
Description
MSM7617
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