msm7716p Oki Semiconductor, msm7716p Datasheet
msm7716p
Related parts for msm7716p
msm7716p Summary of contents
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... Single Rail Linear CODEC GENERAL DESCRIPTION The MSM7716P is an extended temperature range version for the MSM7716 which is a single-channel CODEC CMOS IC for voice signals that contains filters for linear A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, the device is optimized for applications for the analog interfaces of audio signal processing DSPs and digital wireless systems ...
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... LPF BPF ADCONV AUT O ZERO VR GEN SW3 RC 5th 14BIT VOL LPF LPF DACONV SW4 PWD Logic PWD SG SW CONT VOL CONT SW3 SG FEDL7716P-01 MSM7716P PCMOUT T CONT SYNC BCLK PLL RT IM RCONT PCMIN PDN DEN CONT Logic CDIN DCLK VDD AG DG 2/23 ...
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... AG 2 AUXO 3 AOUT+ AOUT– PWI 6 VFO DCLK CDIN DEN connect pin 30-Pin Plastic SSOP FEDL7716P-01 MSM7716P 30 SGC 29 PBIN 28 PBO MAO 24 MAIN PDN 20 SYNC BCLK 17 PCMOUT 16 PCMI 3/23 ...
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... This ground is separated from the analog signal ground in this device. The DG pin must be connected to the AG pin on the printed circuit board. MAO R1 : variable MAIN R2 > 20 k – C1 > 3. R3) (F) + Gain = R2/R1 < variable PBO R4 > 20 k PBIN – C2 > 3. R3) (F) + Gain = R4/R3 < FEDL7716P-01 MSM7716P 4/23 ...
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... The frequency is equal to the data rate. Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the power-saving state. above and below the signal ground voltage when the digital signal with a high impedance /2), can drive a load of a minimum with DD /2) in the high impedance state. DD FEDL7716P-01 MSM7716P /2) in the high DD 5/23 ...
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... The top of the data (MSD) is identified at the rising edge of SYNC. The input signal should be input in the 14-bit 2’s complement format. The MSD bit represents the polarity of the signal with respect to the signal ground. the SYNC frequency values to be actually used FEDL7716P-01 MSM7716P 6/23 ...
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... Connect a 0.1 F capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. Table 1 PCMIN/PCMOUT exceeds 3 FEDL7716P-01 MSM7716P 7/23 ...
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... The control data is shifted at the rising edge of the DCLK signal and latched into the internal control register at the rising edge of the DEN signal. When the microcontroller interface is not used, these pins should be connected to DG. The bit map of the 8-bit control register is shown below SW1 SW2 SW3 SW4 — VOL1 FEDL7716P-01 MSM7716P B1 B0 VOL2 VOL3 8/23 ...
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... DEN DCLK, See Fig See Fig See Fig Transmit gain stage, Gain = 0 dB –100 Transmit gain stage, Gain = 20 dB –10 SYNC, BCLK — FEDL7716P-01 MSM7716P Rating Unit –0.3 to +7.0 V –0 +0 –0 +0 –55 to +150 °C Typ ...
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... SYNC, BCLK OFF Power-down mode, PDN = 0 — 0.45V IH SYNC, BCLK, PCMIN, DEN, CDIN, DCLK, PDN 0.0 IL — — — — PCMOUT pull-up resistor = 500 0.0 — — — — IN FEDL7716P-01 MSM7716P Typ. Max. Unit — 100 — 100 ns — 100 — 100 Typ. Max. Unit 10.0 17.0 mA 8.0 13.0 6 ...
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... SG VFO with respect Output open — AUXO, AOUT+, AOUT–, VFO –1.0 with respect to SG AUXO, AOUT+, AOUT–, VFO –100 with respect to SG FEDL7716P-01 MSM7716P Typ. Max. Unit — — M — — k — — ...
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... FEDL7716P-01 MSM7716P Typ. Max. Unit — — — +0.4 dB — +0.4 — +0.4 — 1.6 — — — +0.2 dB — +0.2 — +0.2 — 0.8 — +0.2 — +0.2 dB — +0.2 — 0.8 — — ...
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... Analog 1020 –40 to –0.3 Analog –50 –1.3 –55 –1.6 3 –0.3 –10 Reference 1020 –40 –0.3 –50 –0.6 –55 –1.2 3 –0.3 –10 Reference 1020 –40 –0.3 –50 –0.6 –55 –1.2 FEDL7716P-01 MSM7716P Typ. Max. Unit +0.01 +0.4 0.00 +0.8 dB –0.03 +1.3 –0.15 +1.6 +0.01 +0.3 dB 0.00 +0.3 –0.03 +0.6 +0.15 +1.2 –0.06 +0.3 –0.02 +0.3 dB –0.02 +0.6 –0.27 +1.2 13/23 ...
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... 1020 0 BCLK = 64 kHz T1 500 T2 600 to 2600 2800 R1 500 to 2600 2800 TRANSRECV 1020 0 RECVTRANS FEDL7716P-01 MSM7716P Min. Typ. Max. Unit — –70 –66 dBm0p — –71 –67 dBm0p — –76 –74 0.350 0.362 Vrms 0.500 0.518 –0.2 — +0.2 dB – ...
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... VFO to AUXO Set at –4 dB –5 –8 dB –9 –12 dB –13 1020 0 –16 dB –17 Referenced –20 dB –21 setting –24 dB –25 –28 dB –29 FEDL7716P-01 MSM7716P Typ. Max. Unit 32 — dB –37.5 –35 dBm0 –52 –40 dBm0 30 — +1.0 dB –4 –3 –8 –7 –12 – ...
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... D9 D10 D11 D12 D13 D14 XD1 . WSL D10 D11 D12 D13 D14 CDH DCH t WCH t CDH t CDS FEDL7716P-01 MSM7716P XD3 . 16/23 ...
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... AUXO Output SG SG PWI PWI DA Table 4 Receive Signal Gain 0 dB –4 dB –8 dB –12 dB –16 dB –20 dB –24 dB –28 dB FEDL7716P-01 MSM7716P Remarks — At initial setting — Remarks — At initial setting — — Remarks At initial setting — — — — — — — 17/23 ...
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... PDN PWI 20 k AOUT AOUT AUXO DCLK 0.1 F DEN SGC CDIN FEDL7716P-01 MSM7716P +3.3V PCM output PCM input PCM shift clock input 8 kHz SYNC pulse input Power down control input “1” = Operation “0” = Power down Controller /2 offset level. DD 18/23 ...
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... FEDL7716P-01 MSM7716P D11 D12 D13 D14 19/23 ...
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... V even instantaneously to avoid latch-up that may otherwise DD occur when power is turned on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices. FEDL7716P-01 MSM7716P 20/23 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL7716P-01 MSM7716P (Unit: mm) Package material Epoxy resin Lead frame material ...
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... OKI Semiconductor REVISION HISTORY Document Date No. FEDL7716P-01 Jun. 17, 2004 Page Previous Current Edition Edition – – First edition FEDL7716P-01 MSM7716P Description 22/23 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL7716P-01 MSM7716P Copyright 2004 Oki Electric Industry Co., Ltd. 23/23 ...