ml7074a-004 Oki Semiconductor, ml7074a-004 Datasheet - Page 18

• Manufacturer Part Number: ml7074a-004
• Description: Voip Codec
• Manufacturer: Oki Semiconductor

This is the output pin for the analog signal ground potential. The output potential at this pin will be about 1.4 V.
These are the pins for either connecting the crystal oscillator for the master clock or for inputting an external master
The oscillations of the master clock oscillator will be stopped during a power down due to the PDNB signal or
This is the power down control input pin. The power down mode is entered when this pin goes to “0”. In addition,
Further, it is possible to carry out a power down reset of the LSI when the power is being supplied by performing
The READY signal (CR5-B7) goes to “1” about 1.0 second after the power down mode is released thereby entering
Notice: At the time of switching on the power, start from the power down mode using PDNB.
These are power supply pins. DV
These are ground pins. GDND0, 1, 2 are the ground pins for the digital circuits and AGND is the ground pin for the
Connect a 2.2 to 4.7 µF (aluminum electrolytic type) capacitor and a 0.1 µF (ceramic type) capacitor in parallel
between this pin and the GND pin as bypass capacitors. The output at the AVREF pin goes to 0.0 V in the power
down mode. The voltage starts rising after the power down mode is released (PDNB = “1” and also CR0-B7 = “0”).
The rise time is about 0.6 seconds.
clock signal.
during a software power down due to CR0-B7 (SPDN). The oscillations start when the power down condition is
released, and the internal clock supply of the LSI will be started after counting up the oscillation stabilization
period (of about 16 ms). Examples of crystal oscillator connection and external master clock input are shown in
Fig. 10.
this pin also has the function of resetting the LSI. In order to prevent wrong operation of the LSI, carry out the
initial power-down reset after switching on the power using this PDNB pin. Also, keep the PDNB pin at “0” level
for 1 µs or more to initiate the power down state.
control of CR0-B7 (SPDN) in the sequence “0” → “1” → “0”.
the mode of setting various functions (initialization mode). See Fig. 1 for the timings of PDNB and AVREF, XO,
and the initialization mode.
power supply pin for the analog circuits of the LSI. Connect these pins together in the neighborhood of the LSI and
connect as bypass capacitors a 10 µF electrolytic capacitor and a 0.1 µF ceramic capacitor in parallel between the
DGND and AGND pins.
analog circuits of the LSI. Connect these pins together in the neighborhood of the LSI.
AVREF
XI, XO
PDNB
DV
DGND0, DGND1, DGND2, AGND
OKI Semiconductor
DD
0, DV
CR0-B7
(SPDN)
PDNB
DD
1, DV
C1
XI
DD
2, AV
Fig. 10 Examples of oscillator circuit and clock input
X'tal
R
DD
C2
DD
0, 1, 2 are the power supply pins for the digital circuits while AV
XO
To internal
circuits
CR0-B7
(SPDN)
PDNB
XI
Daishinku Co., Ltd.
X'tal(4.096 MHz)
4.096 MHz
AT-49
Open
XO
FEDL7074-003DIGEST-01
To internal
circuits
5pF
C1
ML7074-004GA
10pF
C2
DD
1MΩ
R
18/29
is the