fc940l Fairchild Semiconductor, fc940l Datasheet
fc940l
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fc940l Summary of contents
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... Low Voltage Clock Distribution Device with Selectable PECL or LVTTL Input General Description The FC940L low voltage clock fanout buffer. The device allows for the selection of either differential PECL or LVTTL/CMOS input levels. The 18 outputs are compatible with LVCMOS or LVTTL technology and are capable of driving 50 series or parallel terminated lines ...
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... Functional Description The FC940L Clock distribution fanout buffer. The devices accept either a differential PECL or LVCMOS/ LVTTL input signal and generates 18 LVCMOS output sig- nals. The SEL signal selects the differential PECL CLK input signals when held at a logic “L” and selects the LVC- MOS CLK input signal when held at a logic “ ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 2) 0. Input Diode Current ( Output Diode Current (I ) ...
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DC Electrical Characteristics (V Symbol Parameter V High Level Input Voltage PECLK_CLK IH V Low Level Input Voltage PECLK_CLK IL V Peak-to-Peak Input Voltage PP VCMR Common Mode Range (Note 4) V High Level Output Voltage OH V Low Level ...
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AC Loading and Waveforms FIGURE 2. Waveform for Non-Inverting Output Signal FIGURE 3. Waveform for Pin-to-Pin Output Skew dpwh (t FIGURE 5. Output Pulse Width High/Low FIGURE 6. Differential Input Signals Symbol VCCI PECL_CLK 50% of Swing LVC_CLK FIGURE 1. ...
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Physical Dimensions inches (millimeters) unless otherwise noted 32-Lead Thin Quad Flat Package, JEDEC, M0-136, 7mm Square LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL ...