ak4127 AKM Semiconductor, Inc., ak4127 Datasheet - Page 15

• Manufacturer Part Number: ak4127
• Description: 192khz / 24bit High Performance Asynchronous Src
• Manufacturer: AKM Semiconductor, Inc.

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The output port works in master mode or slave mode. The MCLK is not needed in slave mode. The CMODE2-0 pins
select the master/slave and bypass mode. The CMODE2-0 pins should be controlled when the PDN pin = “L”.
The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of OBICK. Select the audio interface format when the
PDN pin = “L”. When in BYPASS mode, both IBICK and OBICK are fixed to 64fs.
When the PLL2-0 pin= “L/H/H”, setting the output port slave (CMODE2-0pin = “H/L/L” or “H/H/L”) enables the TDM
mode at the output port. The OMCLK pin changes to TDMIN pin for TDM data input in TDM mode.
MS0593-E-01
System Clock & Audio Interface Format for Output PORT
Note 15. Changed to TDMIN pin when PLL2-0 pins = “L/H/H”.
Mode
0
1
2
3
4
5
6
7
ILRCK
IBICK(64fs)
SDTI(i)
CMODE
H
H
H
H
L
L
L
L
2
0 1 2
23:MSB, 0:LSB
CMODE
Don't Care
Table 4. Output Audio Interface Format 1 (Output PORT)
H
H
H
H
L
L
L
L
1
Mode
Table 3. Master/Slave Control (Output PORT)
0
1
2
3
CMODE0
8 9
23
Lch Data
H
H
H
H
L
L
L
L
ODIF1
Figure 5. Mode 4 Timing
H
H
L
L
8
24
Master (Bypass)
Slave (Bypass)
Master / Slave
ODIF0
- 15 -
H
H
L
L
Master
Master
Master
Master
Master
Slave
1
31 0 1 2
0
I
SDTO Format
MSB justified
2
LSB justified
Don't Care
S Compatible
(Reserved)
Not used. Set to DVSS.
Not used. Set to DVSS.
Not used. Set to DVSS.
(
(
OMCLK
8 9
Note 15)
Note 15)
256fso
384fso
512fso
768fso
128fso
23
Rch Data
8
24
8k ∼ 108kHz
8k ∼ 108kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
1 0
8k ∼ 54kHz
8k ∼ 54kHz
31
0
fso
1
[AK4127]
2007/07