ak4562 AKM Semiconductor, Inc., ak4562 Datasheet - Page 15

• Manufacturer Part Number: ak4562
• Description: Low Power 20bit Codec With Pga
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n Timing of Control Register
MS0031-E-00
AKM mode
SSB mode
(LSB-first, 5bit) and Control data (LSB-first, 8bit). A side of transmitted data is output to each bit by “ ” of
CCLK, a side of receiving data is input by “ ” of CCLK. Writing of data becomes effective by “ ” of CSN. CSN
should be held to “H” at no access.
Address except 00H 04H inhibits control of writing. And CCLK always need 16 edges of “ ” during CSN =
“L”.
bit (LSB-first, 8bit). Serial clock (SCK) is burst-transmitted, not continuous receiving data. Transmitter outputs
each bit by “ ” of SCK, receiver latches the bit when transmitting the data is input by “ ” of SCK. Writing of data
and command becomes effective by next “ ” of SCK after taking in the last data bit (D7).
Address except 00H 04H inhibits control of writing.
AKM mode is the data in I/F with 3-wire serial control, these data are included by Op-code (3bit), Address
SSB mode is the data in I/F with 2-wire serial interface, these data are included by information bit (3bit) and data
Command Write
Data Write
CSN
CCLK
CDTI
SCK
SSI
op0-op2: Op code (Fixed to “**1:WRITE”)
A0-A4:
D0-D7:
op0 op1
“*”
0
“*”
1
ST:
R/W:
D/C:
D0-D7:
op2
“1”
Figure 12. Control Data Timing (AKM)
2
Figure 13. Control Data Timing (SSB)
Register Address
Control data
ST WR
ST WR
ST R/W
“1”
“1”
A0
0
3
“1”
“1”
A1
4
1
Read/Write bit (Fixed to “1: Write”)
Data/Command bit (0: Data, 1: Command)
Start bit (1: Start)
Address or Control Data
D/C
A2
“1”
“0”
5
C
D
2
A3 A4
D0-D7: Address or Control Data
D0-D3: Device Code, D4-D7: Instruction Code
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
6
- 15 -
3
7
4
D0 D1 D2 D3 D4 D5 D6 D7
8
5
9
6
10 11 12 13 14 15
7
8
9
10
[AK4562]
2000/05