ak4569 AKM Semiconductor, Inc., ak4569 Datasheet - Page 10

• Manufacturer Part Number: ak4569
• Description: 20-bit Stereo Codec With Ipga & Hp-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
(Ta=25°C; AVDD, DVDD, HVDD = 2.5 ∼ 3.6V: C
Note 20. Except AC coupling.
Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to
Note 22. Refer to “Serial Data Interface”.
Note 23. BICK rising edge must not occur at the same time as LRCK edge.
Note 24. The AK4569 can be reset by bringing PDN= “L” to “H” only upon power up.
Note 25. This is the count of LRCK “↑” from PMADC bit=”1”.
MS0292-E-01
Parameter
Master Clock Timing
LRCK Timing
Serial Interface Timing (Note 22)
Control Interface Timing
Power-down & Reset Timing
Frequency
Pulse Width Low
Pulse Width High
AC Pulse Width
BICK Period
BICK Pulse Width Low
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
LRCK to SDTO(MSB)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Frequency
Duty Cycle
CCLK Period
CCLK Pulse Width Low
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
PDN Pulse Width
PMADC “↑” to SDTO valid
ground. (Refer to Figure 4.)
Pulse Width High
Pulse Width High
(Note 20)
(Note 20)
(Note 21)
(Note 24)
(Note 23)
(Note 23)
(Note 25)
SWITCHING CHARACTERISTICS
L
= 20pF)
Symbol
tBCKH
tCCKH
tCLKH
tBCKL
tCCKL
tCLKL
tACW
tCSW
fCLK
tBCK
tCCK
tCDH
tLRB
tBLR
tBSD
tSDH
tCDS
tCSH
tPDV
tLRS
tSDS
tCSS
Duty
tPD
fs
- 10 -
0.4/fCLK
0.4/fCLK
0.4/fCLK
2.048
325.5
min
130
130
200
150
150
45
50
50
50
50
80
80
40
40
50
50
8
2081
44.1
typ
24.576
max
48
55
80
80
[AK4569]
Units
2005/07
MHz
kHz
1/fs
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns