ak4524 AKM Semiconductor, Inc., ak4524 Datasheet - Page 21

• Manufacturer Part Number: ak4524
• Description: 24bit 96khz Audio Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
M0050-E-03
Addr
Addr
01H
02H
RSTDA: DAC reset
RSTDA: ADC reset
DFS1-0: Sampling Speed Control (see Table 2)
CMODE, CKS1-0: Master Clock Frequency Select (see Table 1)
DIF2-0: Audio data interface modes (see Table 4)
0: Reset
1: Normal Operation
0: Reset
1: Normal Operation
000: Mode 0
001: Mode 1
010: Mode 2
011: Mode 3
100: Mode 4
Register Name
Reset Control
Register Name
Clock and Format Control
The internal timing is reset by “0” and then the AOUTs go VCOM voltage immediately. The OATTs also
go “00H”. But the contents of all register are not initialized and enabled to write to the registers. After
The internal timing is reset by “0” and then SDTO goes “L” immediately. The IPGAs also go “00H”. But
the contents of all register are not initialized and enabled to write to the register. After exiting the power
down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, ADCs
output “0” during first 516 LRCK cycles.
Initial: Normal speed
Initial: 256fs
Initial: 24bit MSB justified for both ADC and DAC
RESET
exiting the power down mode, the OATTs fade in the setting value of the control register (06H & 07H).
The analog outputs should be muted externally as some pop noise may occur when entering to and exiting
from this mode.
RESET
DIF2
D7
D7
0
0
0
DIF1
D6
D6
0
0
1
- 21 -
DIF0
D5
D5
0
0
0
CMODE
D4
D4
0
0
0
CKS1
D3
D3
0
0
0
CKS0
D2
D2
0
0
0
RSTAD
DFS1
D1
D1
0
0
[AK4524]
2004/01
RSTDA
DFS0
D0
D0
0
0