ak4520a AKM Semiconductor, Inc., ak4520a Datasheet
ak4520a
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ak4520a Summary of contents
Page 1
... Dynamic Range: 100dB at 5V, 96dB S/N: 100dB at 5V, 96dB at 3V High Jitter Tolerance Sample Rate Ranging from 16kHz to 54kHz Master Clock: 256fs or 384fs 2.7 to 3.6V or 4.5 to 5.5V supply Low Power Dissipation: 255mW Small 28pin VSOP Package 0163-E-00 100dB 20Bit Stereo General Description Features - 1 - [AK4520A] AK4520A ADC & DAC 1997/3 ...
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... ASAHI KASEI Ordering Guide AK4520A-VF AKD4520 Pin Layout 0163-E-00 -10 +70 C 28pin VSOP AK4520A Evaluation Board - 2 - [AK4520A] 1997/3 ...
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... Master Clock Select Pin "H": 384fs, "L": 256fs 26 AOUTL O Lch analog output pin 27 AOUTR O Rch analog output pin 28 VCOM O Common Voltage Output Pin, VA/2 Note: All input pins except pull-down pins should not be left floating. 0163-E-00 PIN/FUNCTION Function - 3 - [AK4520A] 1997/3 ...
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... Note All voltages with respect to ground The power up sequence between VA and VD is not critical. 0163-E-00 ABSOLUTE MAXIMUM RATINGS Symbol min VA -0.3 VD -0.3 GND - IIN - VINA -0.3 VIND -0.3 Ta -10 Tstg -65 Symbol min VA 2.7 VD 2.7 VA 4 [AK4520A] max Units 6.0 V 6.0 V 0.3 V ±10 mA VA+0.3 V VD+0 150 typ max Units 3.0 3 5.0 5.5 V 5.0 VA ...
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... VA= VA= VA=5V 94 100 VA= VA=5V 94 100 90 110 0.1 20 VA=3V 1.7 1.8 VA=5V 2.85 3 VA= VA= VA= VA=5V 96 100 VA= VA=5V 96 100 90 110 0.1 20 VA=3V 1.76 1.88 VA=5V 2.94 3. [AK4520A] max Units 20 Bits 0.3 dB ppm/ C 1.9 Vpp 3.15 Vpp Bits 0.3 dB ppm/ C 1.99 Vpp 3.32 Vpp 1997/3 ...
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... FILTER CHARACTERISTICS Symbol min typ 24. 29 0.9 2 14.7 FR ±0 [AK4520A] max Units 0.4 mA max Units 19.76 kHz 20.02 kHz 20.20 kHz 22.05 kHz kHz dB ±0.005 dB 1/ 20.0 kHz 22.05 kHz kHz ± ...
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... PWAD & PWDA Pulse Width PWAD " " to SDTO valid (Note 13 ) Notes: 11.If the duty cycle of LRCK changes larger than 5 to 50%, the AK4520A is reset by the internal phase circuit automatically. 12.SCLK rising edge must not occur at the same time as LRCK edge. 13.These cycles are the number of LRCK rising from PWAD rising. ...
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... ASAHI KASEI Timing Diagram 0163-E- [AK4520A] 1997/3 ...
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... ASAHI KASEI System Clock Input The AK4520A with CMODE is used to select either MCLK=256fs or 384fs. The relationship between the external clock applied to the MCLK input and the desired sample rate is defined in Table 1 . The LRCK clock input must be synchronized with MCLK, however the phase is not critical. Internal timing is synchronized to LRCK upon power-up or when the internal timing becomes out of phase. All external clocks must be present unless both PWDA and PWAD =" ...
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... ASAHI KASEI 0163-E- [AK4520A] 1997/3 ...
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... ASAHI KASEI Digital High Pass Filter The ADC of AK4520A has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at fs=44.1kHz and also scales with sampling rate(fs). De-emphasis filter The DAC of AK4520A includes the digital de-emphasis filter(tc=50/15us) by IIR filter. This filter corresponds to three frequencies (32kHz,44.1kHz,48kHz). The de-emphasis filter selected by DEM0 and DEM1 is enabled for input audio data. The de-emphasis is also disabled at DEM0=" ...
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... ASAHI KASEI Power-Down & Reset The ADC and DAC of AK4520A are placed in the power-down mode by bringing each power down pin, PWAD PWDA "L" independently and each digital filter is also reset at the same time. This reset should always be done after power-up. In case of the ADC, an analog initialization cycle starts after exiting the power-down mode. ...
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... Figure 6 shows the system connection diagram. This is an example which analog signal is input by single ended circuit. In case of differential input, please refer to Figure evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. 0163-E-00 SYSTEM DESIGN - 13 - [AK4520A] 1997/3 ...
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... AGND and DGND of the AK4520A should be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4520A as possible, with the small value ceramic capacitor being the nearest. ...
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... A simple RC filter(fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs. The AK4520A has tone noise with around -110dB on the ADC output. There are two methods of dropping adding a small DC offset at the ADC input to reduce the noise level. The evaluation board(AKD4520) manual should be referred about the detail ...
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... DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. Figure 10 shows the example of external op-amp circuit with 6dB gain. The output signal is inverted by using the circuit in this case. Figure 10 . External analog circuit example(gain=6dB) 0163-E- [AK4520A] 1997/3 ...
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... ASAHI KASEI 28pin VSOP (Unit: mm) Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: 0163-E-00 PACKAGE Epoxy Cu Solder plate - 17 - [AK4520A] 1997/3 ...
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... ASAHI KASEI XXXBYYYYC date code identifier XXXB: Lot number(X:Digit number, B:Alpha character) YYYYC: Assembly date(Y:Digit number,C:Alpha character) 0163-E-00 MARKING - 18 - [AK4520A] 1997/3 ...
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IMPORTANT NOTICE These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability ...