gal20xv10 Lattice Semiconductor Corp., gal20xv10 Datasheet - Page 11

• Manufacturer Part Number: gal20xv10
• Description: High-speed E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Output Load Conditions (see figure)
Note: fmax with external feedback is calculated from measured
tsu and tco.
3-state levels are measured 0.5V from steady-state active
level.
f
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
C
A
B
Test Condition
Active High
Active Low
Active High
Active Low
f
max with External Feedback 1/(
LOGIC
ARRAY
LOGIC
ARRAY
t
su +
f
t
max with No Feedback
su
t
h
300
300
300
R
1
REGISTER
REGISTER
CLK
CLK
390
390
390
390
390
R
3ns 10% – 90%
2
t
t
GND to 3.0V
su+
co
See Figure
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
11
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
FROM OUTPUT (O/Q)
UNDER TEST
Specifications GAL20XV10
*C
f
max with Internal Feedback 1/(
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
LOGIC
ARRAY
R
2
t
cf
t
+5V
pd
REGISTER
CLK
R
1
t
C *
su+
L
t
TEST POINT
cf)