isplsi2064v-80lj84 Lattice Semiconductor Corp., isplsi2064v-80lj84 Datasheet - Page 7

• Manufacturer Part Number: isplsi2064v-80lj84
• Description: 3.3v High Density Programmable Logic
• Manufacturer: Lattice Semiconductor Corp.

Note: Calculations are based on timing specifications for the ispLSI 2064V-100L.
Derivations of
ispLSI 2064V Timing Model
GOE 0,1
Ded. In
Y0,1,2
I/O Pin
Reset
(Input)
t
4.6 ns
t
0.7 ns
t
10.1 ns
su
h
co
I/O Delay
#21
#20
=
=
=
=
=
=
=
=
=
=
=
=
t
I/O Cell
su,
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.2 + 0.7 + 7.5) + (0.1) - (0.2 + 0.7 + 3.0)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.2 + 0.7 + 4.4) + (3.8) - (0.2 + 0.7 + 7.5)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.2 + 0.7 + 4.4) + (1.5) + (1.4 + 1.9)
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
Reg 4 PT Bypass
io +
t
#33, 34,
XOR Delays
orp +
Control
PTs
#25, 26, 27
Feedback
t
grp +
20 PT
t
35
grp +
#24
Comb 4 PT Bypass #23
7
t
ob)
OE
RE
CK
t
ptck(min))
t
20ptxor)
Specifications ispLSI 2064V
GLB
1
GLB Reg Bypass
D
RST
Table 2-0042/2064V
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2064
#38,
39
I/O Cell
(Output)
I/O Pin