ht82k95ee Holtek Semiconductor Inc., ht82k95ee Datasheet - Page 12

• Manufacturer Part Number: ht82k95ee
• Description: Ht82k95ee/ht82k95ae -- Usb Multimedia Keyboard Encoder 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . But in the
HALT mode, the overflow will initialize a warm reset
and only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are employed; external reset
(a low level to RES), software instruction and a HALT
instruction. The software instruction include CLR
WDT and the other set
WDT2 . Of these two types of instruction, only one can
be active depending on the ROM code option
WDT times selection option . If the CLR WDT is se-
lected (i.e. CLRWDT times equal one), any execution of
the CLR WDT instruction will clear the WDT. In the
case wherein CLR WDT1 and CLR WDT2 are cho-
sen (i.e. CLRWDT times is equal to two), these two in-
structions must be executed to clear the WDT,
otherwise, the WDT may reset the chip as a result of
time-out.
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following:
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on I/O ports or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PDF flags are
examined, the cause for chip reset can be determined.
The PDF flag is cleared by a system power-up or exe-
cuting the CLR WDT instruction and is set when exe-
Rev. 1.20
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on-chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
WS2
0
0
0
0
1
1
1
1
WS1
0
0
1
1
0
0
1
1
WDTS (09H) Register
WS0
0
1
0
1
0
1
0
1
CLR WDT1 and CLR
Division Ratio
1:128
1:16
1:32
1:64
1:1
1:2
1:4
1:8
CLR
12
cuting the HALT instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and SP, the others remain
in their original status.
The I/O ports wake-up and interrupt methods can be
considered as a continuation of normal execution. Each
bit in the Port A can be independently selected to wake
up the device by option. PB, PC and PD can also be se-
lected to wake up the device by option. Upon awakening
from an I/O port stimulus, the program will resume exe-
cution of the next instruction. If it awakens from an inter-
rupt, two sequence may occur. If the related interrupt is
disabled or the interrupt is enabled but the stack is full,
the program will resume execution at the next instruc-
tion. If the interrupt is enabled and the stack is not full,
the regular interrupt response takes place. If an interrupt
request flag is set to 1 before entering the HALT mode,
the wake-up function of the related interrupt will be dis-
abled. Once a wake-up event occurs, it takes 1024 t
(system clock period) to resume normal operation. In
other words, a dummy period will be inserted after a
wake-up. If the wake-up results from an interrupt ac-
knowledge signal, the actual interrupt subroutine execu-
tion will be delayed by one or more cycles. If the wake up
results in the next instruction execution, this will be exe-
cuted immediately after the dummy period is completed.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the initial condition when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
chip resets .
TO PDF
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
0
u
0
1
1
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
HT82K95EE/HT82K95AE
RESET Conditions
August 28, 2006
SYS