ht82k95e Holtek Semiconductor Inc., ht82k95e Datasheet - Page 11

• Manufacturer Part Number: ht82k95e
• Description: Ht82k95e/ht82k95a -- Usb Multimedia Keyboard Encoder 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMIbit.
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), USB interrupt request flag (USBF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en-
able USB interrupt bit (EUI) and enable master interrupt
bit (EMI) constitute an interrupt control register (INTC)
which is located at 0BH in the data memory. EMI, EUI,
ETI are used to control the enabling/disabling of inter-
rupts. These bits prevent the requested interrupt from
being serviced. Once the interrupt request flags (TF,
USBF) are set, they will remain in the INTC register until
the interrupts are serviced or cleared by a software in-
struction.
It is recommended that a program does not use the
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Oscillator Configuration
There is an oscillator circuits in the microcontroller.
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
Rev. 2.00
CALL subroutine within the interrupt subroutine. In-
No.
a
b
c
USB interrupt
Timer/Event Counter 0 overflow
Timer/Event Counter 1 overflow
Interrupt Source
System Oscillator
Priority Vector
1
2
3
0CH
04H
08H
Watchdog Timer
11
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. In stead of
a crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 31 s. The WDT oscillator can
be disabled by ROM code option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (sys-
tem clock divided by 4), determines the ROM code op-
tion. This timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by ROM code option. If the
Watchdog Timer is disabled, all the executions related
to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator, nor-
mally with a period of 31 s/5V) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out
period of 8ms/5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 1s/5V. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. The high nibble and bit 3 of the WDTS are re-
served for user s defined flags, which can only be set to
If the device operates in a noisy environment, using the
on-chip 32kHz RC oscillator (WDT OSC) is strongly rec-
ommended, since the HALT will stop the system clock.
10000 (WDTS.7~WDTS.3).
HT82K95E/HT82K95A
April 16, 2008