ht82k94e Holtek Semiconductor Inc., ht82k94e Datasheet - Page 20

• Manufacturer Part Number: ht82k94e
• Description: Ht82k94e/ht82k94a -- Usb Multimedia Keyboard Encoder 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

MISC register combines a command and status to control desired endpoint FIFO action and to show the status of the
desired endpoint FIFO. The MISC will be cleared by USB reset signal.
The MCU can communicate with the endpoint FIFO by setting the corresponding registers, of which address is listed in
the following table. After reading the current data, next data will show after 2 s, used to check the endpoint FIFO status
and response to MISC register, if read/write action is still going on.
Rev. 1.90
Func. Name
Bit No.
CRC_ERR
0
1
2
4
3
5
6
7
EOT
NMI
Registers
FIFO0
FIFO1
FIFO2
FIFO3
READY
CLEAR
SELP1
SELP0
SCMD
Label
LEN0
REQ
TX
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W Clear the requested endpoint FIFO, even if the endpoint FIFO is not ready.
R/W
R/W
R/W
R
This bit is used to indicate there are CRCerror (bit=1). Firmware must do something to
save the device and keep it in good condition.
This bit is set by SIE and cleared by F/W.
End of transaction flag, normal status is 1. If suspend= 1 line & EOT= 0 indicates that
something is wrong in the USB Interface. Firmware in-charge must do something to
save the device and keep it in good condition.
This bit is used to control whether the USB interrupt is output to the MCU in NAK re-
sponse to the PC Host IN or OUT token.
1: has only USB interrupt, data is transmitted to the PC host or data is received from
the PC Host
0: always has USB interrupt if the USB accesses FIFO0
Default 0
After setting the other status of the desired one in the MISC, endpoint FIFO can be
requested by setting this bit to 1 . After the job has been done, this bit has to be
cleared to 0 .
This bit defines the direction of data transferring between MCU and endpoint FIFO.
When the TX is set to 1 , this means that the MCU wants to write data to the end-
point FIFO. After the job has been done, this bit has to be cleared to 0 before termi-
nating request to represent the end of transferring. For reading action, this bit has to
be cleared to 0 to represent that MCU wants to read data from the endpoint FIFO
and has to be set to 1 after the job is done.
Defines which endpoint FIFO is selected, SELP1,SELP0:
00: endpoint FIFO0
01: endpoint FIFO1
10: endpoint FIFO2
11: endpoint FIFO3
Used to show that the data in endpoint FIFO is a SETUP command. This bit has to
be cleared by firmware. That is to say, even the MCU is busy, the device will not miss
any SETUP commands from the host.
Read only status bit, this bit is used to indicate that the desired endpoint FIFO is
ready to work.
Used to indicate that a 0-sized packet is sent from a host to the MCU. This bit should
be cleared by firmware.
R/W
R/W
R/W
R/W
R/W
MISC (46H) Register
SIES Function
Bank
20
1
1
1
1
Description
Function
Address
4AH
4BH
48H
49H
HT82K94E/HT82K94A
Data7~Data0
Data7~Data0
Data7~Data0
Data7~Data0
Bit7~Bit0
April 29, 2008