adum3210 Analog Devices, Inc., adum3210 Datasheet - Page 5

• Manufacturer Part Number: adum3210
• Description: Dual-channel Digital Isolator, Enhanced System-level Esd Reliability
• Manufacturer: Analog Devices, Inc.

ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ V
apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at T
Table 3.
Parameter
DC SPECIFICATIONS
SWITCHING SPECIFICATIONS
1
2
3
4
5
6
7
8
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Figure 4
total V
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
load within the recommended operating conditions.
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on
opposing sides of the isolation barrier.
CM
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See
information on per-channel supply current for unloaded and loaded conditions. See the
current for a given data rate.
PHL
PSK
Input Supply Current, per Channel, Quiescent
Output Supply Current, per Channel, Quiescent
ADuM3210TR, Total Supply Current, Two Channels
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
Propagation Delay Skew
Channel-to-Channel Matching
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Common-Mode Transient Immunity
Refresh Rate
Input Dynamic Supply Current, per Channel
Output Dynamic Supply Current, per Channel
H
is the magnitude of the worst-case difference in t
propagation delay is measured from the 50% level of the falling edge of the V
Change vs. Temperature
at Logic High Output
at Logic Low Output
DC to 2 Mbps
10 Mbps
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
DD1
V
V
V
V
through
DD1
DD2
DD1
DD2
and V
Supply Current
Supply Current
Supply Current
Supply Current
DD2
Figure 6
supply currents as a function of data rate.
4
3
2
for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See
7
7
5
PLH
− t
PHL
6
|
4
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
8
8
1
PHL
and/or t
Ix
signal to the 50% level of the rising edge of the V
Symbol
I
I
I
I
I
I
I
V
V
V
V
V
V
PW
t
PWD
t
t
t
|CM
|CM
f
I
I
DDI (Q)
DDO (Q)
DD1 (Q)
DD2 (Q)
DD1 (10)
DD2 (10)
IA
r
DDI (D)
DDO (D)
PHL
PSK
PSKCD
R
IH
IL
OAH
OBH
OAL
OBL
/t
, I
F
, t
PLH
IB
H
L
|
|
PLH
that is measured between units at the same operating temperature, supply voltages, and output
DD1
Rev. A | Page 5 of 20
Min
−10
0.7 × (V
or V
(V
V
(V
V
10
20
25
25
DD2
DD2
DD1
DD1
≤ 3.6 V, 3.0 V ≤ V
DD2
) − 0.1
) − 0.5
or
or
)
DD1
Ix
signal to the 50% level of the falling edge of the V
Power Consumption
Typ
0.3
0.3
0.8
0.7
2.0
1.1
+0.01
3.0
2.8
0.0
0.04
0.2
5
3.0
35
35
1.1
0.10
0.03
O
DD2
> 0.8 V
Max
3
0.5
0.5
1.3
1.0
3.2
1.7
+10
0.3 × (V
or V
0.1
0.1
0.4
100
60
22
3
≤ 3.6 V. All minimum/maximum specifications
DD2
DD2
Ox
)
DD1
. CM
signal.
section for guidance on calculating per-channel supply
L
is the maximum common-mode voltage slew rate
Unit
mA
mA
mA
mA
mA
mA
μA
V
V
V
V
V
V
V
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
kV/μs
kV/μs
Mbps
mA/Mbps
mA/Mbps
Figure 4
Power Consumption
A
= 25°C, V
Ox
Test Conditions
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
0 ≤ V
I
I
I
I
I
C
C
C
C
C
C
C
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
Ox
Ox
Ox
Ox
Ox
signal. t
L
L
L
L
L
L
L
L
Ix
Ix
through
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= 15 pF, CMOS signal levels
= V
= 0 V, V
= −20 μA, V
= −4 mA, V
= 20 μA, V
= 400 μA, V
= 4 mA, V
IA
Figure 7
DD1
, V
, V
PLH
IB
DD1
CM
, ≤ V
Figure 6
DD2
propagation delay is
ADuM3210
= 1000 V,
Ix
= V
Ix
, V
and
Ix
= V
DD1
Ix
Ix
= V
CM
= V
= V
= V
section. See
DD2
IxL
= 1000 V,
or V
IxL
Figure 8
for
IxH
IxL
IxH
= 3.0 V.
DD2
for