zl2005 Intersil Corporation, zl2005 Datasheet

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... PCB. The ZL2005 is designed flexible building block for DC power and can be easily adapted to designs ranging from a single-phase power supply operating from a 3.3 V input to a multi-phase supply operating from input ...

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... Table of Contents 1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Typical Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ZL2005 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Power Conversion Overview 4.3 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... DGND SGND PGND SGND Junction temperature Storage temperature range Lead temperature (soldering ESD HBM tolerance (100 pF, 1.5 kΩ) 3 ZL2005 Pin(s) VDD DLY(0,1), EN, ILIM(0,1), MGN, PG, SA(0,1), SALRT, SCL, SDA, SS(0,1), SYNC, TACH, UVLO, V(0,1) ISENB, VSEN, VTRK, XTEMP, ISENA VR V25 BST GH GL ...

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... Current sense input bias current NOTE: 1. Percentage of Full Scale (F.S.) with temperature compensation applied Current sense input bias current (V referenced, OUT V <= 3.6V) OUT Soft start delay duration range Soft start delay duration accuracy 4 ZL2005 Symbol V tied to V (Figure floating (Figure OUT T J Θ ...

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... Switching frequency setpoint accuracy Maximum PWM duty cycle Minimum SYNC pulse width Input clock frequency drift tolerance Tachometer Characteristics TACH pulse width TACH frequency range TACH accuracy 5 ZL2005 - +85 C. Typical values are Condition Set using SS pin or resistor 2 Configurable via I ...

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... Low-side driver peak gate drive current (pull-down) Low-side driver pull-up resistance Low-side driver pull-down resistance Switching timing GH rise and fall time GL rise and fall time Tracking VTRK input bias current VTRK tracking threshold 6 ZL2005 - +85 C. Typical values are Condition ( 4.5 V BST ...

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... + τ 1 switching frequency Automatically set to same value as soft start ramp time 7 ZL2005 - +85 C. Typical values are Condition Factory default 2 Configurable via I C/SMBus Factory default Factory default Factory default 4 Set using pin-strap or resistor ...

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... Current limit select. Sets the overcurrent threshold voltage for ISENA, ISENB. Serial clock. Connect to external host and/or to other ZL2005s. Serial data. Connect to external host and/or to other ZL2005s. Serial alert. Connect to external host if desired. Loop compensation selection pins. ...

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... PWM loop gain ZL2005 Soft start pins. Set the output voltage ramp time during turn-on and turn-off. Tracking sense input. Used to track an external voltage source. Output voltage feedback. Connect to output regulation point. ...

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... ILIM1 7 SCL ™ I C/SMBus 2 8 SDA 9 SALRT Notes: 1. Conditions 1.8 V, Freq = 400 kHz OUT 2 2. The I C/SMBus requires pullup resistors. Please refer to the I 10 ZL2005 VR 10 µF C V25 µF BAT54 16 V VIN 27 CB BST PGND 23 ...

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... Once enabled, the ZL2005 is immediately ready to regulate power and perform power management tasks with no programming required. The ZL2005 can be configured by simply connecting its pins according to the tables provided in this document. Advanced con- figuration options and real-time configuration changes ...

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... ADC ADC MUX Figure 5. ZL2005 Detailed Block Diagram In its most simple configuration, the ZL2005 requires two external N-channel power MOSFETs, one for the top control MOSFET (QH) and one for the bottom synchronous MOSFET (QL). The amount of time that fraction of the total switching period is ...

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... See Application Note AN13 for SW more details on SMBus monitoring. 4.4 Multi-mode Pins In order to simplify circuit design, the ZL2005 incor- porates patented multi-mode pins that allow the user to easily configure many aspects of the device without requiring the user to program the IC. Most power man- agement features can be configured using these pins ...

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... A total of 25 unique selections are available using a single resistor C/SMBus Settings: Almost any ZL2005 function can be configured via the I standard PMBus commands. Additionally, any value that has been configured using the pin-strap or resistor setting methods can also be re-configured and/or veri- fied via the I for details ...

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... Power Conversion Functional Description 5.1 Internal Bias Regulators and Input Supply Connections The ZL2005 employs two internal low dropout (LDO) regulators to supply bias voltages for internal circuitry, allowing it to operate from a single input supply. The internal bias regulators are as follows: VR: The VR LDO provides a regulated 5V bias supply for the MOSFET driver circuits ...

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... The output voltage may also be set to any value between 0.6V and 5.5V using the I face. See Application Note AN13 for details. 5.4 Start-up Procedure The ZL2005 follows a specific internal start-up proce- 34.8 kΩ dure after power is applied to the VDD pin. Table 8 38.3 kΩ describes the start-up sequence. ...

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... Table 8. ZL2005 Start-up Sequence Step # Step Name 1 Power Applied Input voltage is applied to the ZL2005’s VDD pin Internal The device will check for values stored in its internal memory. 2 Memory Check This step is also performed after a Restore command. Multi-mode 3 The device loads values configured by multi-mode pins. ...

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... ZL2005 for asserting PG are met to when the PG pin is actually asserted. This feature is commonly used instead of using an external reset con- troller to control external digital logic. By default, the ZL2005 PG delay is set equal to the soft-start ramp R or DLY time setting. Therefore, if the soft-start ramp time is ...

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... Table 13. Switching Frequency Selection SYNC Pin Setting If the user wishes to run the ZL2005 at a frequency other than those listed in Table 13, the switching fre- quency can be set using an external resistor, R connected between SYNC and SGND using Table 14. ...

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... Table 14. The difference is due to hardware quantization. 5.8 Selecting Power Train Components The ZL2005 is a synchronous buck controller that uses external MOSFETs, inductor and capacitors to per- form the power conversion process. The proper selec- tion of the external components is critical for optimized performance ...

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... Since this calculation is specific to each inductor and manufac- turer, refer to the chosen inductor’s datasheet. Add the 21 ZL2005 core loss and the DCR loss and compare the total loss to the maximum power dissipation recommendation in ) equal to the the inductor datasheet ...

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... MOSFETs with lower R gate charge requirements, which increases the current and resulting power required to turn them on and off. Since the MOSFET gate drive circuits are integrated in the ZL2005, this power is dissipated in the ZL2005 according to the following equation: QH Selection In addition to the R QH also has switching loss. The procedure to select QH is similar to the procedure for QL. First, assign 2– ...

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... I is the peak gate drive current available from the gdr ZL2005. Although the ZL2005 has a typical gate drive current use the minimum guaranteed current for a conservative design. Using the calculated switching time, calculate the switching power loss in QH using = × ...

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... To set the current limit threshold, the user must first select a current sensing method. The ZL2005 incorpo- rates two methods for current sensing, synchronous MOSFET R sensing and inductor DC resistance DS(ON) (DCR) sensing ...

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... NOTES: 1. The number of violations allowed prior to issuing a fault response. 25 ZL2005 Current Sensing Method Ground-referenced (R ) sensing DS,ON Best for low duty cycle and low f Blanking time: 672 ns Best for low duty cycle and high f Blanking time: 352 ns ...

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... R LIM0 28.7 kΩ 31.6 kΩ 34.8 kΩ Figure 15. Control Loop Block Diagram In the ZL2005, the compensation zeros are set by con- 38.3 kΩ figuring the FC0 and FC1 pins or via the I 42.2 kΩ interface once the user has calculated the required set- 46.4 kΩ tings. This method eliminates the inaccuracies due to 51.1 kΩ ...

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... NLR circuitry to force a negative cor- rection signal that will turn on the lower MOSFET and quickly force the output to decrease. The ZL2005 has been pre-configured with appropriate NLR settings that correspond to the loop compensa- tion settings in Table 21. FC1 Pin > ...

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... Efficiency Optimized Driver Dead- time Control The ZL2005 utilizes a closed loop algorithm to opti- mize the dead-time applied between the gate drive sig- nals for the top and bottom FETs synchronous buck converter, the MOSFET drive circuitry must be designed such that the top and bottom MOSFETs are never in the conducting state at the same time ...

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... Power Management Functional Description 6.1 Input Undervoltage Lockout (UVLO) The input undervoltage lockout (UVLO) prevents the ZL2005 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. The UVLO threshold (V can be set between 2.85 V and 16 V using the UVLO pin ...

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... See Section 6.2, “Output Overvoltage Protection,” for response options due to an overvoltage condition. 6.4 Output Overcurrent Protection The ZL2005 can protect the power supply from dam- age if the output is shorted to ground overload condition is imposed on the output. Once the current limit threshold has been selected (see Section 5.9, “ ...

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... I C/SMBus interface. 6.5 Thermal Protection The ZL2005 includes an on-chip thermal sensor that continuously measures the internal temperature of the die and will shut down the device when the tempera- ture exceeds the preset limit. The default temperature limit is set to 125°C in the factory, but the user may set the limit to a different value if desired ...

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... Limited by VTRK pin voltage 110% Ω of V(0,1) pin-strap setting 19 ZL2005 The master ZL2005 device in a tracking group is defined as the device that has the highest target output voltage within the group. This master device will con- trol the ramp rate of all tracking devices and is not V OUT configured for tracking mode ...

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... Voltage Margining The ZL2005 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. The MGN pin is a TTL-compatible input that is con- tinuously monitored and can be driven directly by a processor I/O pin or other logic-level output. The ZL2005’ ...

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... Output Sequencing 18 56.2 kΩ 19 61.9 kΩ A group of ZL2005 devices may be configured to 20 68.1 kΩ power predetermined sequence. This feature kΩ especially useful when powering advanced processors, FPGAs, and ASICs that require one supply to reach its 22 82.5 kΩ ...

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... Event based sequencing and fault spreading are broad- cast in address groups eight ZL2005 devices. An address group consists of all devices whose 35 ZL2005 addresses differ in only the three least significant bits of the address ...

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... Embedded Thermal Diode Figure 18. External Temperature Monitoring 6.14 Fan Monitoring using the TACH Pin The ZL2005 can monitor the tachometer pulse of an external 3-wire fan connected to the TACH pin. The device will report a revolutions per minute (RPM) value assuming one pulse per revolution. The TACH ...

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... ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE, RESPECTIVELY. 6. MAXIMUM PACKAGE WARPAGE IS 0.05 mm. 7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS. 8. PIN # TOP WILL BE LASER MARKED. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 10. THIS DRAWING CONFORMS TO JEDEC REGISTERED OUTLINE MO-220. 37 ZL2005 FN6848.0 February 18, 2009 ...

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... The following application support documents and tools are available to help simplify your design. Item ZL2005EVK1 Evaluation Kit: 12V to 3.3V, 20A DC/DC Converter with Power Management AN10 Application Note: ZL2005 and ZL2105 Thermal and Layout Guidelines AN11 Application Note: ZL2005 Component Selection Guide AN13 Application Note: PMBus Command Set ...

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... ANY USE THEREOF. Any use of such reference designs is at your own risk and you agree to indem- nify Intersil Corporation and it's subsidiaries including Zilker Labs, Inc. for any damages resulting from such use. 39 ZL2005 Zilker Labs, Inc. 4301 Westbank Drive Building A-100 ...