rt9262a ETC-unknow, rt9262a Datasheet - Page 8

• Manufacturer Part Number: rt9262a
• Description: High Efficiency, Supply Current, Step-up Dc/dc Converter
• Manufacturer: ETC-unknow

RT9262/A
Application Note
Output Voltage Setting
Referring to application circuits Fig.1 to Fig.5, the
output voltage of the switching regulator (V
be set with Eq.1.
The LDO output voltage (V
set with Eq.2.
And trip point of the low battery detector is 0.86V at
LBI pin of RT9262A.
Feedback Loop Design
Referring to application circuits Fig.1 to Fig.5, The
selection of R1, R2, R3, and R4 based on the trade-
off between quiescent current consumption and
interference immunity is stated below:
• Follow Eq.1 and Eq.2.
• Higher R reduces the quiescent current (Path
• Lower R gives better noise immunity, and is less
• A proper value of feed forward capacitor parallel
For applications without standby or suspend modes,
lower values of R1 to R4 are preferred. For
applications concerning the current consumption in
standby or suspend modes, the higher values of R1
to R4 are needed. Such “high impedance feedback
loops” are sensitive to any interference, which require
careful layout and avoid any interference, e.g.
probing to FB/LFB pins.
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current = 1.25V/R2, and 0.86V/R3), however
resistors beyond 5MΩ are not recommended.
sensitive to interference, layout parasitics, FB/LFB
node leakage, and improper probing to FB/LFB
pins.
with R1 (or R4) on Fig.1 to Fig.5 can improve the
noise immunity of the feedback loops, especially in
an improper layout. An empirical suggestion is
around 100pF ~ 1nF for feedback resistors of MΩ,
and 10nF ~ 0.1µF for feedback resistors of tens to
hundreds KΩ.
V
V
OUT
OUT
2
1
=
=
1 (
1 (
+
+
R
R
R
R
1
2
3
4
)
)
×
×
. 1
. 0
25
86
OUT2
V
V
of RT9262) can be
OUT1
) can
Eq.2
Eq.1
Preliminary
PRECAUTION 1: Improper probing to FB or LFB pin
will cause fluctuation at V
damage RT9262/A and system chips because V
may drastically rise to an over-rated level due to
unexpected interference or parasitics being added to
FB pin.
PRECAUTION 2: Disconnecting R1 or short circuit
across R2 may also cause similar IC damage as
described in precaution 1.
PRECAUTION 3: When large R values were used in
feedback loops, any leakage in FB/LFB node may
also cause V
IC damage. To be especially highlight here is when
the air moisture frozen and re-melt on the circuit
board may cause several µA leakage between IC or
component pins. So, when large R values are used in
feedback loops, post coating, or some other
moisture-preventing processes are recommended.
Layout Guide
•
•
•
•
•
•
connection for C2 to Pin1 and Pin6.
capacitor close to L1 inductor, when VIN is not an
idea voltage source.
far away from noise sources.
and EXT nodes, which may cause additional
switching loss.
board layout for application circuits Fig.1 to Fig.4.
A full GND plane without gap break.
V
V
Minimized FB/LFB node copper area and keep
Minimized parasitic capacitance connecting to LX
The following diagram is an example of 2-layer
OUT1
IN
to GND noise bypass – Add a 100µF
Q
+
Prober Parasitics
_
to GND noise bypass – Short and wide
OUT1
and V
OUT2
OUT1
DS9262/A-04 August 2002
voltage fluctuation, and
V
and V
OUT1
R2
R1
OUT2
FB Pin
. It may
OUT1