net2890 ETC-unknow, net2890 Datasheet - Page 23

• Manufacturer Part Number: net2890
• Description: Interface Controller
• Manufacturer: ETC-unknow

Specification
4.5.3 Isochronous Endpoints
Isochronous endpoints are used for the transfer of time critical data. Isochronous transfers do not support
any handshaking or error checking protocol, and are guaranteed a certain amount of bandwidth during each
frame. The Serial Interface Engine in the NET2890 ignores CRC and bit stuffing errors during isochronous
transfers, but sets the EPUSBSTAT handshaking bits the same as for non-isochronous packets so that the
local CPU can detect errors. Isochronous endpoints are unidirectional, with the direction defined by the
endpoint configuration registers.
The maximum packet size of an Isochronous endpoint can be larger than the 128 byte FIFOs in the
NET2890. For an Isochronous OUT endpoint, the local CPU or DMA reads data from the FIFO at the
same time that data is being received from the USB. The local CPU or DMA must be able to read data fast
enough from the FIFO to prevent an overflow. The FIFO Almost Full Threshold can also be used to
prevent overflows by interrupting the CPU when the FIFO is almost full.
For an Isochronous IN endpoint, the local CPU or DMA writes data to the FIFO at the same time that data
is being transmitted to the USB. The local CPU or DMA must be able to write data fast enough to the FIFO
to prevent an underflow. The FIFO Almost Empty Threshold can also be used to prevent underflows by
interrupting the CPU when the FIFO is almost empty.
4.5.3.1 Isochronous Out Transactions
Isochronous Out endpoints are used to transfer data from a USB host to the NET2890 local bus. An
Isochronous OUT transaction consists of the following:
The USB host initiates an Isochronous OUT transaction by sending an OUT token to an Isochronous OUT
endpoint. The Data OUT Token Interrupt status bit is set when the OUT token is recognized. If this
interrupt is enabled, the local interrupt IRQ# pin is asserted. The bytes corresponding to the Data stage are
stored into the endpoint’s FIFO. If the FIFO is full when another byte is transferred from the host, the byte
will be discarded and the USB OUT NAK Sent status bit will be set, even though a NAK is not actually
sent to the host for isochronous packets. No handshake packets are returned to the host, but the USB OUT
ACK Sent, USB OUT NAK Sent, and Timeout status bits are still set to indicate the status of the
transaction. After every data packet is received, the local CPU should sample these status to determine if
the packet was successfully received by the host.
By definition, isochronous endpoints do not utilize handshaking with the host. Since there is no way to
return a stall acknowledge from an isochronous endpoint to the host, data which is sent to a stalled
isochronous endpoint will be received normally.
The local CPU can either start polling for valid data immediately after receiving the OUT token, or can wait
for the Data Packet Received Interrupt status bit to be set. If it waits for the interrupt, then the Maximum
Packet Size must be less than the FIFO size. As the FIFO is filling up from the USB side, the local CPU
can poll the FIFO Empty status bit to determine when a byte is available. Otherwise it can either poll the
Data Packet Received Interrupt status bit, or enable it as an interrupt, and then read the entire packet
from the FIFO at once. The FIFO almost full interrupt can also be used by the local CPU to determine
when to start reading Isochronous OUT data from the FIFO. The local CPU can either poll the FIFO
Almost Full Interrupt status bit, or enable it to generate a local interrupt by asserting IRQ#.
____________________________________________________________________________________
Stage
OUT Token
Data
335 Pioneer Way, Mountain View, California 94041
TEL [phone] FAX [phone]
Packet Contents
OUT PID, address, endpoint, and CRC5
DATA0 PID, N data bytes, and CRC16
NetChip Technology, Inc., 1999
Rev 2.0, Draft 9, July 16, 1999
http://www.netchip.com
NET2890 USB Interface Controller
bytes
N+3
# of
3
Source
Host
Host
23