wm8325gefl/v Wolfson Microelectronics plc, wm8325gefl/v Datasheet - Page 16

• Manufacturer Part Number: wm8325gefl/v
• Description: Processor Power Management Subsystem
• Manufacturer: Wolfson Microelectronics plc

WM8325
SYSTEM CONTROL AND SUPERVISION
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GPIOS
The WM8325 has 12 general-purpose input/output (GPIO) pins, GPIO1 - GPIO12. These can be
configured as inputs or outputs, active high or active low, with optional on-chip pull-up or pull-down
resistors. GPIO outputs can either be CMOS driven or Open Drain configuration. Each GPIO pin can
be tri-stated and can also be used to trigger Interrupts. The function of each GPIO pin is selected
individually. Different voltage power domains are selectable on a pin by pin basis for GPIOs 1-12,
see Table 2.
Table 2 GPIO Power Domains
In addition to the default inputs and outputs, GPIOs have a wide range of secondary input and output
functions. Input functions include power state change requests, DVS requests and hardware control
of regulator modes. Outputs include functions such as power state notifications, 32kHz clock, DVS
complete and system power or converter power good flags.
INTERRUPTS
The WM8325 has a comprehensive Interrupt logic capability. The dedicated IRQ
alert a host processor to selected events or fault conditions. Each of the interrupt conditions can be
individually enabled or masked. Following an interrupt event, the host processor should read the
interrupt registers in order to determine what caused the interrupt, and take appropriate action if
required.
The WM8325 interrupt controller has two levels:
Secondary interrupts indicate a single event in one of the circuit blocks. The event is indicated by
setting a register bit. This bit is a latching bit - once it is set, it remains at logic 1 even if the trigger
condition is cleared. The secondary interrupts are cleared by writing a logic 1 to the relevant register
bit. Note that reading the register does not clear the secondary interrupt.
Primary interrupts are the logical OR of the associated secondary interrupts (usually all the interrupts
associated with one particular circuit block). Each of the secondary interrupts can be individually
masked or enabled as an input to the corresponding primary interrupt.
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GPIO1, GPIO2, GPIO3
GPIO4, GPIO5, GPIO6
GPIO7, GPIO8, GPIO9
GPIO10, GPIO11, GPIO12
I
Output fault monitoring on all regulator outputs (overcurrent or undervoltage) with
programmable fault action
Programmable system undervoltage (UV) level
Chip thermal monitor and programmable warning level interrupt
Watchdog timer function
Two-tier interrupts with full masking
Configurable GPIO power domain
GPIO control for regulator functions for lower latency/flexibility
2
C or SPI compatible primary control interface
GPIO
DBVDD
DBVDD
DBVDD
DBVDD
DEFAULT POWER
DOMAIN
Product Brief, February 2011, Rev 1.4
VPMIC (LDO12VOUT)
PVDD
VPMIC (LDO12VOUT)
PVDD
ALTERNATE POWER
¯ ¯ ¯ pin can be used to
DOMAIN
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