wm9711lgefl-v Wolfson Microelectronics plc, wm9711lgefl-v Datasheet - Page 22

• Manufacturer Part Number: wm9711lgefl-v
• Description: Low Power Audio Codec For Portable Applications
• Manufacturer: Wolfson Microelectronics plc

WM9711L
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Table 9 ALC Control
62h
ALC / Noise
Gate Control
60h
ALC Control
REGISTER
ADDRESS
15:14
13:11
10:9
8
15:12
11:8
7:4
3:0
BIT
ALCSEL
MAXGAIN
ZC
TIMEOUT
ALCZC
ALCL
HLD
DCY
ATK
LABEL
00
(OFF)
111
(+30dB)
11
0
1011
(-12dB)
0000
(0ms)
0011
(192ms)
0010
(24ms)
DEFAULT
ALC function select
00 = ALC off (PGA gain set by register)
01 = Right channel only
10 = Left channel only
11 = Stereo (PGA registers unused)
Note: Ensure that RECVOLL and
RECVOLR settings (reg. 1Ch) are the same
before entering this mode.
PGA gain limit for ALC
111 = +30dB
110 = +24dB
….(6dB steps)
001 = -6dB
000 = -12dB
Programmable zero cross timeout
11 2
10 2
01 2
00 2
ALC Zero Cross enable (overrides ZC bit in
register 1Ch)
0: PGA Gain changes immediately
1: PGA Gain changes when signal is zero or
after time-out
ALC target – sets signal level at ADC input
0000 = -28.5dB FS
0001 = -27.0dB FS
… (1.5dB steps)
1110 = -7.5dB FS
1111 = -6dB FS
ALC hold time before gain is increased.
0000 = 0ms
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.691s
ALC decay (gain ramp-up) time
0000 = 24ms
0001 = 48ms
0010 = 96ms
… (time doubles with every step)
1010 or higher = 24.58s
ALC attack (gain ramp-down) time
0000 = 6ms
0001 = 12ms
0010 = 24ms
… (time doubles with every step)
1010 or higher = 6.14s
17
16
15
14
x MCLK period
x MCLK period
x MCLK period
x MCLK period
DESCRIPTION
PD Rev 4.3 August 2006
Production Data
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