71m6532f-igt Maxim Integrated Products, Inc., 71m6532f-igt Datasheet - Page 16

• Manufacturer Part Number: 71m6532f-igt
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

meter equations. This assistance is controlled through I/O RAM location EQU[2:0] (equation assist). The
Compute Engine (CE) firmware for residential configurations implements the equations listed in
EQU[2:0] specifies the equation to be used based on the number of phases used for metering.
locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the
digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled
with the RTM_E bit. The RTM output is clocked by CKTEST (pin SEG19/CKTEST), with the clock output
enabled by setting CKOUT_E = 1. Each RTM word is clocked out in 35 cycles and contains a leading flag
bit. See
YPULSE, as well as increased hardware support for the two original pulse generators (RPULSE and
WPULSE). The pulse generators can be used to output CE status indicators, SAG for example, to DIO pins.
The polarity of the pulses may be inverted with the PLS_INV bit. When this bit is set, the pulses are active
high, rather than the more usual active low. PLS_INV inverts all the pulse outputs.
XPULSE and YPULSE
Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse outputs. Pins DIO8
and DIO9 are used for these pulses. Generally, the XPULSE and YPULSE outputs are updated once on
each pass of the CE code, resulting in a pulse frequency up to a maximum of 1260Hz (assuming a MUX
frame is 13 CK32 cycles).
The YPULSE pin can be used by the CE code to generate interrupts based on sag events. This method
is faster than checking the sag bits by the MPU at every CE_BUSY interrupt. See Section
and Control
RPULSE and WPULSE
During each CE code pass, the hardware stores exported WPULSE AND RPULSE sign bits in an 8-bit
FIFO and outputs them at a specified interval. This permits the CE code to calculate the RPULSE and
WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX
frame. The FIFO is reset at the beginning of each MUX frame. The PLS_INTERVAL register controls the
delay to the first pulse update and the interval between subsequent updates. Its LSB is 4 CK_FIR cycles.
If zero, the FIFO is deactivated and the DFFs are updated immediately. Thus, N
4 * PLS_INTERVAL.
Data Sheet 71M6531D/F-71M6532D/F
1.3.1
The 71M6531D/F and 71M6532D/F provide hardware assistance to the CE in order to support various
1.3.2
The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM
1.3.3
The 71M6531D/F and 71M6532D/F provide four pulse generators, RPULSE, WPULSE, XPULSE and
16
EQU[2:0]
0
1
2
Not all CE codes support all equations.
Meter Equations
Real-Time Monitor
Pulse Generators
Figure 20
for details.
1 element, 2 W,
1φ with neutral
current sense
1 element, 3 W,
1φ
2 element, 3 W,
3φ Delta
Description
for the RTM output format. RTM is low when not in use.
© 2005-2010 TERIDIAN Semiconductor Corporation
Element
VA · IA
VA · IA
VA(IA-
IB)/2
Watt and VAR Formula
0
Table 5: Meter Equations
Element
VA · IB
VB · IB
N/A
1
Element
N/A
N/A
N/A
2
SLOTn_SEL[3:0]
programmable
Sequence is
Sequence
Mux
with
INTERVAL
SLOTn_ALTSEL[3:0]
programmable with
FDS 6531/6532 005
Sequence is
4.3.6 CE Status
Sequence
ALT Mux
is
Table
v1.3
5.