sc16is741ipw NXP Semiconductors, sc16is741ipw Datasheet - Page 33

• Manufacturer Part Number: sc16is741ipw
• Description: Single Uart With I2c-bus/spi Interface, 64 Bytes Of Transmit And Receive Fifos, Irda Sir Built-in Support
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16IS741_1
Product data sheet
Fig 16. A complete data transfer
SDA
SCL
condition
START
10.2 Addressing and transfer formats
S
There are two exceptions to the ‘acknowledge after every byte’ rule. The first occurs when
a master is a receiver: it must signal an end of data to the transmitter by not signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock, generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.
The second exception is that a slave will send a negative acknowledge when it can no
longer accept additional data bytes. This occurs after an attempted transfer that cannot be
accepted.
Each device on the bus has its own unique address. Before any data is transmitted on the
bus, the master transmits on the bus the address of the slave to be accessed for this
transaction. A well-behaved slave with a matching address, if it exists on the network,
should of course acknowledge the master's addressing. The addressing is done by the
first byte transmitted by the master after the START condition.
An address on the network is seven bits long, appearing as the most significant bits of the
address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is
transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete
data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is
shown in
When an address is sent, each device in the system compares the first seven bits after
the START with its own address. If there is a match, the device will consider itself
addressed by the master, and will send an acknowledge. The device could also determine
if in this transaction it is assigned the role of a slave receiver or slave transmitter,
depending on the R/W bit.
Each node of the I
microcontroller is of course fully programmable, while peripheral devices usually have
fixed and programmable address portions.
When the master is communicating with one device only, data transfers follow the format
of
transfer and issuing a STOP condition, if a master would like to address some other
device on the network, it could start another transaction by issuing a new START.
address
Figure
0 to 6
Figure
16, where the R/W bit could indicate either direction. After completing the
R/W
7
16.
ACK
2
8
C-bus network has a unique seven-bit address. The address of a
Single UART with I
Rev. 01 — 29 April 2010
0 to 6
data
7
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
ACK
8
0 to 6
data
7
SC16IS741
ACK
8
© NXP B.V. 2010. All rights reserved.
condition
STOP
P
002aab046
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