ts512mkr72v3nl Transcend Information. Inc., ts512mkr72v3nl Datasheet - Page 6

• Manufacturer Part Number: ts512mkr72v3nl
• Description: 240pin Ddr3 1333 Vlp Registered Dimm 4gb With 256mx8 Cl9 Placement
• Manufacturer: Transcend Information. Inc.

IDD Specification parameters Definition
Transcend Information Inc.
( IDD values are for full operating range of Voltage and Temperature)
T
Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other
control and address bus inputs are STABLE; Data bus inputs are FLOATING
T
T
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),
tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;
Note:
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL =
CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is
HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control
and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT =
0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL
= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is
HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING IDD4R
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;
BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD),
tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid
commands;Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R;
S
S
S
5
5
5
1. Module I
1
1
1
2
2
DQ loading capacitor.
2
M
M
M
K
K
K
DD
R
R
R
was calculated on the basis of component I
7
7
7
2
2
2
V
V
V
Parameter
3
3
3
N
N
N
L
L
L
6
240PIN DDR3 1333 VLP Registered DIMM
DD
and can be differently measured according to
Symbol
IDD4W
IDD2Q
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD0
IDD1
IDD5
IDD6
IDD7
4GB With 256Mx8 CL9
1,934
2,024
1,664
1,150
1,150
1,844
2,609
2,654
3,104
3,284
Max.
970
816
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA