ts32mls64v8d Transcend Information. Inc., ts32mls64v8d Datasheet - Page 9

• Manufacturer Part Number: ts32mls64v8d
• Description: 168pin Pc100 Unbuffered Dimm 256mb With 16m X 8 Cl3
• Manufacturer: Transcend Information. Inc.

Transcend information Inc.
SIMPLIFIED TRUTH TABLE
T
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Clock Suspend or
Active
Down
Precharge Power
Down Mode
DQM
No Operation Command
Note: 1. OP Code: Operand Code
T
T
S
S
S
2. MRS can be issued only at both banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA
5. During burst read or write with auto precharge, new read/write command cannot be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
3
3
3
2
A
A new command can be issued after 2 CLK cycles of MRS.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
If both BA
If both BA
If both BA
If both BA
If A
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
2
Power
2
0
0
~BA
~A
10
M
M
COMMAND
M
11
/AP is “High” at row precharge, BA
1
, BA
: Bank select address.
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
Entry
Exit
Entry
Exit
L
L
L
0
0
0
0
0
and BA
and BA
is “Low” and BA
is “High” and BA
~BA
S
S
S
1
: Program keys. (@MRS)
6
6
6
1
1
Entry
Exit
are “Low” at read, write, row active and precharge, bank A is selected.
are “High” at read, write, row active and precharge, bank D is selected.
4
4
4
V
V
V
1
1
is “High” at read, write, row active and precharge, bank B is selected.
is “Low” at read, write, row active and precharge, bank C is selected.
8
8
8
D
D
CKEn-1 CKEn
D
H
H
H
H
H
H
H
H
H
H
H
L
L
L
0
and BA
X
H
H
X
X
X
X
X
H
H
X
L
L
L
1
is ignored and both banks are selected.
/CS
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
9
/RAS
H
H
H
H
V
H
V
H
L
L
X
L
L
X
X
X
X
X
X
/CAS
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
168PIN PC100 Unbuffered DIMM
/WE
H
H
H
H
H
H
L
X
L
L
L
X
V
X
X
X
V
X
DQM
X
X
X
X
X
X
X
X
X
X
X
X
V
X
256MB With 16M X 8 CL3
BA
V
V
V
V
X
0,1
OP CODE
A
10
Row Address
H
H
H
X
X
X
X
X
X
X
L
L
L
/AP
A
Address
Address
Column
(A
Column
(A
A
0
0
0
X
~A
11
~A
~A
,
9
9
9
)
)
Note
4, 5
4, 5
1,2
3
3
3
3
4
4
6
7