m34282m1 Renesas Electronics Corporation., m34282m1 Datasheet
m34282m1
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m34282m1 Summary of contents
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... FEATURES • Number of basic instructions ............................................. 68 • Minimum instruction execution time ............................ 8.0 s (at f 4.0 MHz, system clock = f(X IN • Supply voltage ................................................. 1 3.6 V • Subroutine nesting ..................................................... 4 levels ROM (PROM) size Part number M34282M1-XXXGP M34282M2-XXXGP M34282E2GP PIN CONFIGURATION (TOP VIEW ...
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Group BLOCK DIAGRAM Rev.1.33 Mar 18, 2004 page ...
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... Group PERFORMANCE OVERVIEW Parameter Number of basic instructions Minimum instruction execution time Memory sizes ROM M34282M2/E2 M34282M1 RAM M34282M2/E2 M34282M1 Input/Output D –D Output 0 3 ports D –D I –E Input Output –G I CARR Output Timer Timer 1 Timer 2 Subroutine nesting ...
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Group CONNECTIONS OF UNUSED PINS Connection Pin Open or connect – Set the output latch to “1” and open connect to V pin (Note 2). DD Open or ...
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Group PORT BLOCK DIAGRAMS Decoder Register Y SD instruction RD instruction CLD instruction Register Y Decoder SD instruction RD instruction CLD instruction Skip decision (SZD instruction) Key-on wakeup Register (Note 3) OEA T instruction ...
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Group FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, and bit manipulation. (2) Register A and carry flag Register 4-bit register ...
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Group (5) Most significant ROM code reference enable flag (URS) URS flag controls whether to refer to the contents of the most significant 1 bit (bit 8) of ROM code when executing the TABP p instruction. If URS flag ...
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Group (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read binary counter that increments the number ...
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... Fig. 11 RAM map Subroutine special page RAM 64 words 4 bits (256 bits Register words M34282M2/E2 Page 0 Page 1 Page 2 Page 3 Page 15 48 words M34282M1 ...
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Group TIMERS The 4282 Group has the programmable timer. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set decremented from a setting value n. When it underflows ...
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Group V1 (Note CARRY 1 1 Reload register R1 (8) (TAB1) Register (Note 1/2 1 (TAB2) CAR flag SCAR instruction RCAR instruction ...
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Group Table 4 Control registers related to timer Timer control register V1 V1 Carrier wave output auto-control bit 2 V1 Timer 1 count source selection bit 1 Timer 1 control bit V1 0 Timer control register V2 V2 Carrier ...
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Group (3) Timer 1 Timer 8-bit binary down counter with the timer 1 reload register (R1). When timer is stopped, data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB ...
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Group “ 1 ” “ 0 ” “ H ” ...
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Group In this case, the following is set; • To expand “H” interval of carrier wave is invalid (V2 • Timer 2 carrier wave generation function is valid (V2 • Count source X /2 selected (V2 IN • “L” ...
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Group WATCHDOG TIMER Watchdog timer provides a method to reset and restart the system when a program runs wild. Watchdog timer consists of 14-bit timer (WDT) and watchdog timer flags (WDF1, WDF2). Watchdog timer downcounts the instruction clock (INSTCK) ...
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Group RESET FUNCTION The 4282 Group has the power-on reset circuit, though it does not have RESET pin. System reset is performed automatically at power-on, and software starts program from address 0 in page 0. f “H” ...
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Group • Program counter (PC) .............................................................. Address 0 in page 0 is set to program counter. • Power down flag (P) ................................................................. • Timer 1 underflow flag (T1F) ................................................... • Timer 2 underflow flag (T2F) ................................................... • Timer control ...
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Group RAM BACK-UP MODE The 4282 Group has the RAM back-up mode. When the POF instruction is executed, system enters the RAM back-up state. As oscillation stops retaining RAM, the functions and states of reset circuit at RAM back-up ...
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Group (4) Return signal An external wakeup signal is used to return from the RAM back-up mode. Table 8 shows the return condition for each return source. Table 8 Return source and return condition Return source Return condition Ports ...
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Group CLOCK CONTROL The clock control circuit consists of the following circuits. • System clock generating circuit • Control circuit to stop the clock oscillation • Control circuit to return from the RAM back-up state ...
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Group LIST OF PRECAUTIONS Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.01 µ F) between pins V and V at the shortest distance, DD ...
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Group INSTRUCTIONS The 4282 Group has the 68 instructions. Each instruction is described as follows; (1) List of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table SYMBOL The symbols ...
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Group LIST OF INSTRUCTION FUNCTION Mnemonic Function Groupi n g TAB (A) (B) TBA (B) (A) TAY (A) (Y) TYA (Y) (A) TEAB (ER – (ER – TABE (B) (ER –ER ...
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Group Grouping Mnemonic Function (A) = (M(DP)) ? SEAM SEA – ( ( ...
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Group LIST OF INSTRUCTION FUNCTION (CONTINUED) Groupi n g Mnemonic Function (D) 0 CLD RD (D(Y (D(Y SZD (D(Y ( ...
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Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET (Add n and accumulator) Instrunction D 8 code Operation: (A) ( (Add accumulator and Memory) Instrunction D ...
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... A ) determined by replac ing the low-order 4 bits of the address a in page p with register A. Note for M34282M1 for M34282M2/E2. Number of Number of Flag CY words cycles 1 1 – Grouping: Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2 ...
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... Description: Call the subroutine : Calls the subroutine at address ( replacing the low-order 4 bits of address a in page p with register A. Note for M34282M1 for M34282M2/E2. Number of Number of Flag CY words cycles 1 1 – Grouping: Other operation Description: Changes system clock (STCK) from f(X to f(X ) ...
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Group CMA (CoMplement of Accumulator) Instrunction D 8 code Operation: (A) (A) DEY (DEcrement register Y) Instrunction D 8 code Operation: (Y) (Y) – 1 IAE (Input ...
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Group INY (INcrement register Y) Instrunction D 8 code Operation: (Y) ( (Load n in Accumulator) Instrunction D 8 code Operation: (A) n ...
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Group NOP (No OPeration) Instrunction D 8 code Operation: (PC) (PC OEA (Output port E from Accumulator) Instrunction D 8 code Operation ...
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Group RAR (Rotate Accumulator Right) Instrunction D 8 code Operation (Reset Bit) Instrunction D 8 code ...
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Group RD (Reset port D specified by register Y) Instrunction D 8 code Operation: (D(Y)) 0 However, ( (ReTurn from subroutine) Instrunction D 8 code ...
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Group SC (Set Carry flag) Instrunction D 8 code Operation: (CY) 1 SCAR (Set CAR flag) Instrunction D 8 code Operation: (CAR (Set port D ...
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Group SEAM (Skip Equal, Accumulator with Memory) Instrunction D 8 code Operation: (A) = (M(DP)) ? SNZP (Skip if Non Zero condition of Power down flag) Instrunction D 8 code ...
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Group SZB j (Skip if Zero, Bit) Instrunction D 8 code Operation: (Mj(DP SZC (Skip if Zero, Carry flag) Instrunction D 8 code 0 0 ...
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Group T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B) Instrunction D 8 code Operation: (R2L –R2L ) ( (R2L –R2L ) ( (T2 ...
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... H When URS = 0, (B) (ROM(PC When URS = 1, (CY) (ROM(PC)) 8 (B) (ROM(PC (SP) (SP) – 1, (PC) Note for M34282M1 for M34282M2/E2. Rev.1.33 Mar 18, 2004 page ...
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Group TAM j (Transfer data to Accumulator from Memory) Instrunction D 8 code Operation: (A) (M(DP)) (X) (X)EXOR( TAY (Transfer data to Accumulator from register Y) Instrunction D ...
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Group TEAB (Transfer data to register E from Accumulator and register B) Instrunction D 8 code Operation: (ER – (ER – TLOA (Transfer data to ...
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Group TV1A (Transfer data to register V1 from Accumulator) Instrunction D 8 code Operation: (V1 – – TV2A (Transfer data to register V2 from Accumulator) Instrunction ...
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Group WRST (Watchdog timer ReSeT) Instrunction D 8 code Operation: (WDF1) 0 XAM j (eXchange Accumulator and Memory data) Instrunction D 8 code Operation: (A) (M(DP)) (X) ...
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Group MACHINE INSTRUCTIONS (INDEX BY FUNCTION) Parameter Mnemonic instructions TAB TBA TAY TYA ...
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Group Skip condition – – Transfers the contents of register B to register A. – – Transfers the contents of register A to register B. – – Transfers the contents of register Y to register A. – – Transfers ...
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... SZC CMA RAR LGOP Note for M34282M1 for M34282M2/E2. Rev.1.33 Mar 18, 2004 page Instruction code Hexadecimal notation ...
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Group Skip condition Continuous – Loads the value n in the immediate field to register A. description When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously ...
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... BLA Note for M34282M1 for M34282M2/E2. Rev.1.33 Mar 18, 2004 page Instruction code Hexadecimal notation ...
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Group Skip condition – – Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). – – Clears (0) the contents of bit j (bit specified by the value j ...
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... TAB1 TV1A SNZT1 T2AB Note : for M34282M1, and for M34282M2/E2. Rev.1.33 Mar 18, 2004 page Instruction code Hexadecimal notation ...
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Group Skip condition – – Call the subroutine in page 2 : Calls the subroutine at address a in page 2. – – Call the subroutine : Calls the subroutine at address a in page p. – – Call ...
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Group MACHINE INSTRUCTIONS (CONTINUED) Parameter Mnemonic instructions TAB2 TV2A SNZT2 T2HAB 0 1 ...
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Group Skip condition – – Transfers the contents of timer 2 to registers A and B. – – Transfers the contents of register A to registers V2. (T2F – Skips the next instruction when the contents of ...
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Group Parameter Mnemonic instructions NOP POF SNZP CCK TLOA ...
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Group Skip condition – – No operation – – Puts the system in RAM back-up state. ( – Skips the next instruction when P flag is “1.” After skipping, P flag remains unchanged. – – System clock ...
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... SB RB XAMD TABP BML* TPU1A 14 XAMD TABP BML* TPU0A 15* –D show the high-order 5 bits of the machine language cannot be used in the M34282M1 LXY LXY LXY LA LXY 0 0 0,0 1,0 2,0 3,0 LXY LXY LXY LXY A LA 0,1 ...
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Group REGISTER STRUCTURE Timer control register V1 V1 Carrier wave output auto-control bit 2 V1 Timer 1 count source selection bit 1 V1 Timer 1 control bit 0 Timer control register V2 V2 Carrier wave “H” interval expansion bit ...
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Group ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply voltage DD V Input voltage I V Output voltage O P Power dissipation d T Operating temperature range opr T Storage temperature range stg RECOMMENDED OPERATING CONDITIONS (Ta = –20 C ...
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Group ELECTRICAL CHARACTERISTICS (Ta = – unless otherwise noted) DD Symbol Parameter V “L” level output voltage Port CARR OL V “L” level output voltage X OL OUT V “H” level ...
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Group BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4282 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to ...
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Group (1) PROM mode (serial input/output) The M34282E2GP has a PROM mode in addition to a normal operation mode. It has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) ...
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Group (2) Functional outline In the PROM mode, data is transferred with the clock- synchronous serial input/output. The input data is read through the SDA pin into the internal circuit synchronously with the rising edge of the serial clock ...
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Group (4) Program Input command code 25 in the first transfer. Proceed and 16 input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, t ...
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Group PROGRAM ALGORITHM FLOW CHART Rev.1.33 Mar 18, 2004 page START 4V,V = 12. ADRS = first location X=0 WRITE PROGRAM-VERIFY COMMAND WRITE PROGRAM DATA ...
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Group TIMING REQUIREMENT CONDITION AND SWITCHING CHARACTERISTICS ( 4 12 Symbol Parameter t Serial transfer width time CH t Read wait time after transfer CR t Read pulse ...
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Group (6) Notes on handling A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. For the One Time PROM version, Renesas corp. does not perform PROM writing ...
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Group PACKAGE OUTLINE 20P2E/F-A EIAJ Package Code JEDEC Code SSOP20-P-225-0.65 – Detail G 1 Rev.1.33 Mar 18, 2004 page Weight(g) Lead Material 0.08 Alloy 42/Cu Alloy 11 F ...
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REVISION HISTORY Rev. Date Page 1.00 – First edition issued Jul. 23, 2003 1.10 12 (2) Precautions revised. Jul. 25, 2000 13 (3) Timer 1, (4) Timer 2 revised. 22 Timer revised 1.20 7 Character fonts errors revised. Aug. 23, ...
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Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...