mb91307r Fujitsu Microelectronics, Inc., mb91307r Datasheet - Page 68

• Manufacturer Part Number: mb91307r
• Description: 32-bit Microcontroller Cmos Fr60 Mb91307 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

68
MB91307 Series
10. External Interface
(1) Overview
(2) Features
The external interface controller controls the interface between the LSI’s internal bus and external memory or I/
O devices.
This section describes the functions of the external interface.
• Up to 32 bit-length (4G bytes space) address output.
• Connects directly to many external memory (8 bit/16 bit) devices, allows control of multiple access timings.
• 8 independent bank (chip select area) settings, each with corresponding chip select output available
• The following functions can be independently set for each chip select area.
• Different detailed timing settings for each access timing type
• Fly-by transfer with DMA enabled
• External bus arbitration using BRQ and BGRNT enabled
• Pins not used in external interface can be set for use as general purpose I/O ports
Asynchronous SRAM, asynchronous ROM/Flash memory (multiple write strobe type or byte enable type)
Page mode ROM/flash memory (2/4/8 page size enabled)
Burst ROM/Flash memory (MBM29BL160D/161D/162D etc.)
Address/data multiplexed bus (8 bit/16 bit width only)
Synchronous memory* (ASIC built-in memory etc.)
Each area size can be set in multiples of 64K bytes (from 64K bytes to 2G bytes per chip select area).
Each area can be set in any desired area of logic address space (boundaries limited by area size).
Chip select area enable/disable (no access to prohibited areas)
Access timing type for each area, etc.
Detailed access timing settings (individual access type settings for wait cycle, etc.)
Data bus width setting (8 bit/16 bit)
Byte ordering endian setting* (big or little).
Write prohibited setting (read-only areas)
Internal cache loading enable/disable settings
Pre-fetch function enable/disable settings
Maximum burst length setting (1,2,4,8)
Different settings can be used for each chip select area even for the same access timing type.
Auto wait setting up to 15 cycles (asynchronous SRAM, ROM, Flash, I/O areas)
Bus cycle extension with external RDY input enabled (asynchronous SRAM, ROM, Flash, I/O areas)
First access wait and page wait settings enabled (burst, page mode ROM/FLASH areas)
Different idle, recovery cycles setup delay insertion etc. enabled
Transfer between memory and I/O with 1 access
Memory wait cycle can be synchronized with I/O wait cycle during fly-by
Hold time can be obtained by delaying transfer access only
Specific idle/recovery cycles can be set for fly-by transfer
*: Does not connect to synchronous SRAM.
*: CS0 area available with big endian only.