p87c591vfb NXP Semiconductors, p87c591vfb Datasheet - Page 67

• Manufacturer Part Number: p87c591vfb
• Description: Single-chip 8-bit Microcontroller With Can Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
As data bits come in from the right, 1s shift out to the left.
When the start bit arrives at the left most position in the
shift register (which in Mode 1 is a 9-bit register), it flags
the RX Control block to do one last shift, load S0BUF and
RB8, and set RI. The signal to load S0BUF and RB8, and
to set RI, will be generated if, and only if, the following
conditions are met at the time the final shift pulse is
generated:
1. RI = 0, and
2. Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met, the
stop bit goes into RB8, the 8 data bits go into S0BUF, and
RI is activated. At this time, whether the above conditions
are met or not, the unit goes back to looking for a 1-to-0
transition in RxD.
More About Modes 2 and 3
Eleven bits are transmitted (through TxD), or received
(through RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9
the 9
On receive, the 9
baud rate is programmable to either
oscillator frequency in Mode 2. Mode 3 may have a
variable baud rate generated from Timer 1.
Figure 25 show a functional diagram of the serial port in
Modes 2 and 3. The receive portion is exactly the same as
in Mode 1. The transmit portion differs from Mode 1 only in
the 9
Transmission is initiated by any instruction that uses
S0BUF as a destination register. The “write to S0BUF”
signal also loads TB8 into the 9
shift register and flags the TX Control unit that a
transmission is requested. Transmission commences at
S1P1 of the machine cycle following the next rollover in the
divide-by-16 counter. (Thus, the bit times are
synchronized to the divide-by-16 counter, not to the “write
to SUB” signal).
The transmission begins with activation of SEND, which
puts the start bit at TxD. One bit time later, DATA is
activated, which enables the output bit of the transmit shift
register to TxD. The first shift pulse occurs one bit time
after that. The first shift clocks a 1 (the stop bit) into the 9
bit position of the shift register. Thereafter, only zeros are
clocked in. Thus, as data bit shift out to the right, zeros are
clocked in from the left. When TB8 is at the output position
of the shift register, then the stop bit is just to the left of
TB8, and all positions to the left of that contain zeros.
This condition flags the TX Control unit to do one last shift
2000 Jul 26
Single-chip 8-bit microcontroller with CAN controller
th
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data bit (TB8) can be assigned the values of 0 or 1.
bit of the transmit shift register.
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the
data bit, and a stop bit (1). On transmit,
data bit goes into RB8 in SCON. The
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bit position of the transmit
1
16
or
1
32
the
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67
and then deactivate SEND and set TI. This occurs at the
11
Reception is initiated by a detected 1-to-0 transition at
RxD. For this purpose RxD is sampled at a rate of 16 times
whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is
immediately reset, and 1FFH is written to the input shift
register.
At the 7
bit detector samples the value of R-D. The value accepted
is the value that was seen in at least 2 of the 3 samples. If
the value accepted during the first bit time is not 0, the
receive circuits are reset and the unit goes back to looking
for another 1-to-0 transition. If the start bit proves valid, it
is shifted into the input shift register, and reception of the
rest of the frame will proceed.
As data bits come in from the right, 1s shift out to the left.
When the start bit arrives at the left most position in the
shift register (which in Modes 2 and 3 is a 9-bit register), it
flags the RX Control block to do one last shift, load S0BUF
and RB8, and set RI.
The signal to load S0BUF and RB8, and to set RI, will be
generated if, and only if, the following conditions are met
at the time the final shift pulse is generated.
1. RI = 0, and
2. Either SM2 = 0, or the received 9
If either of these conditions is not met, the received frame
is irretrievably lost, and RI is not set. If both conditions are
met, the received 9
data bits go into S0BUF. One bit time later, whether the
above conditions were met or not, the unit goes back to
looking for a 1-to-0 transition at the RxD input.
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divide-by-16 rollover after “write to SUBF”.
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, 8
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, and 9
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data bit goes into RB8, and the first 8
counter states of each bit time, the
Preliminary Specification
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data bit = 1.
P8xC591