atxmega128a4-mu ATMEL Corporation, atxmega128a4-mu Datasheet - Page 7

• Manufacturer Part Number: atxmega128a4-mu
• Description: Atxmega16a4 8/16-bit Avr Xmega Microcontroller
• Manufacturer: ATMEL Corporation

7. Memories
7.1
7.2
7.3
8069A–AVR–02/08
Features
Overview
In-system Programmable Flash Program Memory
•
•
The AVR architecture has two main memory spaces, the Program Memory and the Data Mem-
ory. In addition, the XMEGA A4 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no paging. The memory configurations are shown in
”Ordering Information” on page
Non-volatile memory spaces can be locked for further write and read/write operations. This pre-
vents unrestricted access to the application software.
The XMEGA A4 contains On-chip In-System Re-programmable Flash memory for program stor-
age, see
address location is 16 bits.
The XMEGA A4 has additional Boot section for bootloader applications. The Store Program
Memory (SPM) instruction used to write to the Flash will only operate from this section. Opera-
tion of the SPM is also associated with Boot Lock bits for software protection.
The XMEGA A4 has an Application Table section inside the Application section for storage of
Non-volatile data.
Flash Program Memory
Data Memory
– One linear address space
– In-System Reprogrammable
– Self-Programming and Bootloader support
– Application Section for application code
– Application Table Section for application code or data storage
– Bootloader Section for application code or bootloader code
– Separate lock bits and protection for all sections
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
– I/O Memory
– External Memory
– Bus arbitration
– Separate buses for SRAM, EEPROM, IO Memory and External Memory access
Byte or page accessible
Optional memory mapping for direct Load/Store
Configuration and Status register for all peripherals and modules
16 bit accessible General Purpose Register for global variable or flags
Safe and deterministic handling of CPU and DMA Controller priority
• Enables simulatiouns bus access for CPU and DMA Controller
Table 7-1 on page
8. Since all AVR instructions are 16- or 32-bits wide, each Flash
3.
ATxmega A4
7