hcs166ms Intersil Corporation, hcs166ms Datasheet

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hcs166ms

Manufacturer Part Number
hcs166ms
Description
Radiation Hardened 8-bit Parallel-input/serial Output Shift Register
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current Levels Ii
Description
The Intersil HCS166MS is an 8-bit shift register that has fully
synchronous serial or parallel data entry selected by an
active LOW Parallel Enable (PE) input. When the PE is LOW
one setup time before the LOW-to-HIGH clock transition,
parallel data is entered into the register. When PE is HIGH,
data is entered into internal bit position Q0 from Serial Data
Input (DS), and the remaining bits are shifted one place to
the right (Q0
clock transition. For expansion of the register in parallel to
serial converters, the Q7 output is connected to the DS input
of the succeeding stage.
The clock input is a gated OR structure which allows one
input to be used as an active LOW Clock Enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary and
con be reversed for layout convenience. The LOW-to-HIGH
transition of CE input should only take place while the CP is
HIGH for predictable operation.
A LOW on the Master Reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all bit
positions to a LOW state.
The HCS166MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS166MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Bit-Day (Typ)
- Standard Outputs - 10 LSTTL Loads
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
Q1
Q2m etc.) with each positive-going
10
RAD s(Si)/s 20ns Pulse
5 A at VOL, VOH
12
o
C to +125
RAD (Si)/s
o
C
2
/mg
-9
Errors/
Parallel-Input/Serial Output Shift Register
250
Pinouts
Ordering Information
HCS166DMSR
HCS166KMSR
HCS166D/
Sample
HCS166K/
Sample
HCS166HMSR
GND
NUMBER
DS
CE
CP
D0
D1
D2
D3
PART
HCS166MS
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
16 LEAD CERAMIC DUAL-IN-LINE
16 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
TEMPERATURE
-55
-55
DS
CE
CP
D0
D1
D2
D3
o
o
RANGE
C to +125
C to +125
Radiation Hardened 8-Bit
+25
+25
+25
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
o
o
o
TOP VIEW
TOP VIEW
C
C
C
o
o
C Intersil Class S
C Intersil Class S
Equivalent
Equivalent
Sample
Sample
Die
16
15
14
13
12
11
10
SCREENING
9
16
15
14
13
12
11
10
9
Spec Number
LEVEL
PE
D7
Q7
D6
D5
D4
MR
File Number
VCC
16 Lead
SBDIP
16 Lead
Ceramic
Flatpack
16 Lead
SBDIP
16 Lead
Ceramic
Flatpack
Die
PACKAGE
PE
D7
Q7
D6
D5
D4
MR
VCC
518758
2482.2

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hcs166ms Summary of contents

Page 1

... Input Current Levels VOL, VOH Description The Intersil HCS166MS is an 8-bit shift register that has fully synchronous serial or parallel data entry selected by an active LOW Parallel Enable (PE) input. When the PE is LOW one setup time before the LOW-to-HIGH clock transition, parallel data is entered into the register ...

Page 2

... ENABLE ENABLE High Level L = Low Level X = Immaterial = Transition from low to high level HCS166MS TRUTH TABLE INPUTS PARALLEL CLOCK SERIAL The level of steady state input at inputs D0 thru D7, respectively. ...

Page 3

... Functional Test VIH = 0.70(VCC), VIL = 0.30(VCC), (Note 2) NOTES: 1. All voltages reference to device GND. 2. For functional tests, VO 4.0V is recognized as a logic “1”, and VO Specifications HCS166MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...

Page 4

... The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Specifications HCS166MS GROUP (NOTES 1, 2) ...

Page 5

... AC measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = VCC. 3. For functional tests, VO 4.0V is recognized as a logic “1”, and VO TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH Specifications HCS166MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP ...

Page 6

... Each pin except VCC and GND will have a resistor of 1K OPEN 13 NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCS166MS TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS 100%/5004 ...

Page 7

... Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. HCS166MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...

Page 8

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HCS166MS tf MR ...

Page 9

... D1 (3) D2 (4) D3 (5) CE (6) (7) CP NOTE: The die diagram is a generic plot from a similar HCS device intended to indicate approximate die size and bond pad location. The mask series for the HCS166 is TA14386A. HCS166MS HCS166MS D0 DS VCC (2) (1) (16) (8) (9) (10) GND ...

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