hcs32dmsr Intersil Corporation, hcs32dmsr Datasheet

hcs32dmsr

Manufacturer Part Number

hcs32dmsr

Description

Rad-hard Quad 2-input Or Gate

Manufacturer

Intersil Corporation

Datasheet

1.HCS32DMSR.pdf (11 pages)

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Radiation Hardened Quad 2-Input OR

Gate

The Intersil HCS32MS is a Radiation Hardened Quad 2-Input

OR Gate. A low on both inputs forces the output to a low state.

The HCS32MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of the

radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCS32MS is supplied in a 14 Ld Ceramic flatpack

(K suffix) or a SBDIP Package (D suffix).

Ordering Information

HCS32DMSR Q 5962R95

HCS32KMSR Q 5962R95

HCS32D/

Sample

HCS32K/

Sample

HCS32HMSR

Intersil Pb-free hermetic packaged products employ SnAgCu or Au

termination finish, which are RoHS compliant termination finishes and

compatible with both SnPb and Pb-free soldering operations. Ceramic

dual in-line packaged products (CerDIPs) do contain lead (Pb) in the

seal glass and die attach glass materials. However, lead in the glass

materials of electronic components are currently exempted per the

RoHS directive. Therefore, ceramic dual inline packages with Pb-free

termination finish are considered to be RoHS compliant.

NUMBER

PART

78101VCC

78101VXC

MARKING

PART

-55°C to +125°C 14 Ld SBDIP

-55°C to +125°C 14 Ld Ceramic

RANGE (°C)

TEMP.

+25°C

Data Sheet

Flatpack

14 Ld SBDIP

14 Ld Ceramic

Flatpack

Die

PACKAGE

1-888-INTERSIL or 1-888-468-3774

DWG. #

D14.3

K14.A

PKG.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Features

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200k RAD (Si)

• SEP Effective LET No Upsets: >100 MEV-cm

• Single Event Upset (SEU) Immunity < 2 x 10

• Latch-Up Free Under Any Conditions

• Military Temperature Range: -55°C to +125°C

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

• V

• Input Current Levels I

Functional Diagram

NOTE: L = Logic Level Low, H = Logic level High

Errors/Bit-Day (Typ)

(2, 5, 10, 13)

(1, 4, 9, 12)

= 30% of V

= 70% of V

All other trademarks mentioned are the property of their respective owners.

April 11, 2007

Intersil (and design) is a registered trademark of Intersil Americas Inc.

INPUTS

TABLE 1. TRUTH TABLE

Max

Min

≤ 5µA @ VOL, VOH

HCS32MS

OUTPUTS

(3, 6, 8, 11)

-9

FN3057.1

/mg

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hcs32dmsr Summary of contents

Page 1

... The HCS32MS is supplied Ceramic flatpack (K suffix SBDIP Package (D suffix). Ordering Information PART PART TEMP. NUMBER MARKING RANGE (°C) HCS32DMSR Q 5962R95 -55°C to +125° SBDIP 78101VCC HCS32KMSR Q 5962R95 -55°C to +125° Ceramic 78101VXC HCS32D/ +25°C Sample HCS32K/ +25° ...

Page 2

Pinouts HCS32MS 14 LD SBDIP TOP VIEW GND 7 2 HCS32MS VCC GND HCS32MS 14 ...

Page 3

Absolute Maximum Ratings Supply Voltage (VCC +7.0V Input Voltage ...

Page 4

AC Electrical Performance Characteristics CONDITIONS PARAMETER SYMBOL (NOTES 5, 6) Input to Output TPHL VCC = 4.5V Data to Output TPLH VCC = 4.5V NOTES: 5. All voltages referenced to device GND measurements assume RL = 500Ω, CL ...

Page 5

DC Post Radiation Electrical Performance Characteristics Data to Output TPHL TPLH NOTES: 8. All voltages referenced to device GND measurements assume RL = 500Ω 50pF, Input 3ns, VIL = GND, VIH = ...

Page 6

Total Dose Irradiation CONFORMANCE GROUPS METHOD Group E Subgroup 2 5005 NOTES: 13. Except FN test which will be performed 100% Go/No-Go. Static And Dynamic Burn-In Test Connections OPEN GROUND STATIC BURN-IN I TEST CONNECTIONS (Note 14 ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL TABLE 1. AC VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VIL 0 GND 0 8 HCS32MS AC Load Circuit ...

Page 9

Die Characteristics DIE DIMENSIONS: 87milsx88 mils 2.20mmx2.2mm METALLIZATION: Type: SiAl ± 1k Å Å Metal Thickness: 11k GLASSIVATION: Type: SiO 2 ± 2.6k Å Å Thickness: 13k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: ...

Page 10

Ceramic Metal Seal Flatpack Packages (Flatpack) e PIN NO AREA - 0.004 0.036 - SEATING AND c1 LEAD FINISH BASE PLANE ...

Page 11

... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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