nx2119 Microsemi Corporation, nx2119 Datasheet - Page 13

• Manufacturer Part Number: nx2119
• Description: Synchronous Pwm Controller With Current Limit Protection
• Manufacturer: Microsemi Corporation

tion temperature increases, K is R
dependency. As a result, R
the worst case, in which K approximately equals to 1.4
at 125
tion loss should not exceed package rating or overall
system thermal budget.
duction at the switching transition. The total switching
loss can be approximated.
and T
is switching frequency. Switching loss P
dependent.
ered when choosing the proper power MOSFET.
MOSFET gate driver loss is the loss generated by dis-
charg
circuits.It is proportional to frequency and is defined as:
charge,Q
side gate source voltage.
mum power dissipation of the driver device.
Over Current Limit Protection
achieved by sensing current through the low side
MOSFET. For NX2119, the current limit is decided by
the R
FET is on, and the voltage on SW pin is below 320mV,
the over current occurs. The over current limit can be
calculated by the following equation.
Rev.3.2
04/10/08
is the high side gate source voltage, and V
P
where I
gate
where the R
Switching loss is mainly caused by crossover con-
Also MOSFET gate driver loss should be consid-
where Q
Over current Limit for step down converter is
DSON
P
P
P
P
F
i
This power dissipation should not exceed maxi-
ng the gate capacitor and is dissipated in driver
o
HCON
LCON
TOTAL
SW
which can be found in mosfet datasheet, and F
C according to IRFR3706 datasheet
LGATE
(Q
of the low side mosfet. When synchronous
=I
=I
=P
OUT
HGATE
2
1
OUT
OUT
is the low side MOSFETs gate charge,V
HCON
HGATE
is output current, T
2
2
V
IN
DS(ON)
(1 D) R
D R
V
P
is the high side MOSFETs gate
I
HGS
OUT
LCON
will increases as MOSFET junc-
DS(ON)
Q
T
DS(ON)
SW
LGATE
DS(ON)
K
F
should be selected for
S
V
SW
K
DS(ON)
LGS
is the sum of T
) F
SW
temperature
is frequency
S
LGS
.
is the low
Conduc-
.
...(22)
...(20)
..(21)
HGS
R
S
consideration K=1.5, then
Layout Considerations
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
connection in the top layer with wide, copper filled ar-
eas. The inductor, output capacitor and the MOSFET
should be close to each other as possible. This helps to
reduce the EMI radiated by the power traces due to the
high switching currents through them. Place input ca-
pacitor directly to the drain of the high-side MOSFET, to
reduce the ESR replace the single input capacitor with
two parallel units. The feedback part of the system should
be kept away from the inductor and other noise
sources,and be placed close to the IC. In multilayer PCB
use one layer as power ground plane and have a control
circuit ground (analog ground), to which all signals are
referenced.
separate loop that does not interfere with the more sen-
sitive analog control function. These two grounds must
be connected together on the PC board layout at a single
point.
If MOSFET R
The layout is very important when designing high
Start to place the power components, make all the
The goal is to localize the high current path to a
I
I
SET
SET
K R
K R
320mV
320mV
DSON
DSON
DSON
1.5 9m
320mV
=9m , the worst case thermal
NX2119/2119A
23.7A
13